PCI_Device

module device(address, GNT, CLK, force_req, addressToContact, RESET, REQ, Frame,AD , C_BE, IReady, TReady, DevSel);
    input GNT, CLK, RESET, force_req;
    input [31:0] address, addressToContact;

    output REQ;

    inout [31:0] AD;
    input [3:0] C_BE;
    inout Frame, IReady, TReady, DevSel;

    reg [31:0] mem [9:0];
    wire [31:0] data [2:0]; //contains AA.., BB.., CC..

    integer i = 0;
    integer numberOfTransactions;

    wire [1:0]phasesWire;
    reg [1:0]numberOfPhases;

    integer posEdge = 0; //determines which edge of the clock

    //manually entering data inside device
    assign data[0] = 32'hAA_AA_AA_AA;
    assign data[1] = 32'hBB_BB_BB_BB;
    assign data[2] = 32'hCC_CC_CC_CC;

    //number of data phases depends on device address and contact address according to scenarios
    assign phasesWire= (address == 0 && addressToContact == 1)? 3 : (address == 0 && addressToContact == 2) ? 2 :(address == 1)? 2:(address==2)? 1 :0;

    reg isData; //determines which phase I'm in (address or data)

    reg isMaster = 0; //true when device is master (granted and bus is idle)

    reg REQ_reg;
    assign REQ = REQ_reg;


    reg Frame_reg;
    reg [31:0] AD_reg;
    reg DevSel_reg;
    reg IReady_reg;
    reg TReady_reg;

    //asserting signals when master only
    assign Frame = (isMaster) ? Frame_reg : 1'bz;
    assign AD = (isMaster) ? AD_reg : 32'bz;
    assign IReady = (isMaster) ? IReady_reg : 1'bz;

    //asserting DevSel only when not master
    assign DevSel = (!isMaster) ? DevSel_reg : 1'bz;
    assign Tready = (!isMaster) ? TReady_reg : 1'bz;

    always @(CLK)
    begin
    posEdge = ~posEdge;
        if (posEdge) //on positive edge read values and set flags
        begin
            if (!force_req) //as long as the force_req signal is low keep counting
            begin
                i = i+1;
                REQ_reg = 0;
            end

            else if (i != 0) // if it isn't low save the number of transactions in a register and reset the counter
            begin
                numberOfTransactions = i; //
                i = 0;
            end

            else //for synthesis purpose
                i = 0;

            if (GNT == 0 && Frame && IReady) //bus granted and bus is idle
            begin
                isMaster = 1;
                isData=0; //send address on AD
                numberOfPhases <= phasesWire; //initialize the counter register
            end //if
        end //posEdge

        else //on negative edge write values
        begin
            if (isMaster)
            begin
                Frame_reg = 0;
                if(!isData) //sending address
                begin
                    AD_reg = addressToContact;
                    isData=1;
                end

                else //sending data
                    if(numberOfPhases>0)
                    begin
                        numberOfPhases = numberOfPhases - 1;
                        AD_reg = data[address];
                        IReady_reg = 0;
                        if(numberOfPhases ==0)
                            Frame_reg = 1;
                    end

                    else
                        begin
                        IReady_reg = 1;
                        isMaster=0;
                        end
            end //if (isMaster)

            else //target not master
            begin
                //read from master
                if (AD == address)
                    DevSel_reg = 0;
                    TReady_reg = 1;
            end //slave not master
        end //else negEdge
    end //always
endmodule