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  1. #cpudef "Simple_8b_CPU"
  2. {
  3. #bits 8
  4.  
  5. #tokendef REG
  6. {
  7. A = 0b000
  8. B = 0b001
  9. C = 0b010
  10. D = 0b011
  11. }
  12.  
  13. #tokendef ALS
  14. {
  15. ADD = 0b000
  16. SUB = 0b001
  17. INC = 0b010
  18. DEC = 0b011
  19. AND = 0b100
  20. OR = 0b101
  21. XOR = 0b110
  22. CMP = 0b111
  23. }
  24.  
  25. #tokendef FLAGS
  26. {
  27. Z = 0b00000001
  28. ZA = 0b00000010
  29. ZS = 0b00000100
  30. O = 0b00001000
  31. C = 0b00001000
  32. U = 0b00010000
  33. G = 0b00100000
  34. E = 0b01000000
  35. L = 0b10000000
  36. }
  37.  
  38.  
  39. NOP -> 0b000000 @ 0b00
  40. HLT -> 0b000001 @ 0b00
  41. HALT -> 0b000001 @ 0b00
  42. RET -> 0b000010 @ 0b00
  43. RNA -> 0b000011 @ 0b00
  44. PUSH CD -> 0b000100 @ 0b00
  45. POP CD -> 0b000101 @ 0b00
  46.  
  47. ;------------------------------------------------------------------------------------------
  48. ;------------------------------------------------------------------------------------------
  49. ; REG -> REG
  50. MOV {dest: REG}, {src: REG} -> dest[2:0] @ src[2:0] @ 0b01
  51. LD {dest: REG}, {src: REG} -> dest[2:0] @ src[2:0] @ 0b01
  52.  
  53. ; REG -> MEM IMME
  54. MOV I, {src: REG} -> 0b100 @ src[2:0] @ 0b01 @ 0x00[7:0]
  55. LD I, {src: REG} -> 0b100 @ src[2:0] @ 0b01 @ 0x00[7:0]
  56.  
  57. ; REG -> MEM ADDR
  58. MOV ({dest}), {src: REG} -> 0b101 @ src[2:0] @ 0b01 @ dest[15:0]
  59. LD ({dest}), {src: REG} -> 0b101 @ src[2:0] @ 0b01 @ dest[15:0]
  60.  
  61. ; REG -> MEM ADDR CD
  62. MOV (CD), {src: REG} -> 0b110 @ src[2:0] @ 0b01
  63. LD (CD), {src: REG} -> 0b110 @ src[2:0] @ 0b01
  64.  
  65. ; REG -> MEM ADDR CDB
  66. MOV (CDB), {src: REG} -> 0b111 @ src[2:0] @ 0b01
  67. LD (CDB), {src: REG} -> 0b111 @ src[2:0] @ 0b01
  68.  
  69. ;------------------------------------------------------------------------------------------
  70. ; MEM IMME -> REG
  71. MOV {dest: REG}, {src} -> dest[2:0] @ 0b100 @ 0b01 @ src[7:0]
  72. LD {dest: REG}, {src} -> dest[2:0] @ 0b100 @ 0b01 @ src[7:0]
  73.  
  74. ; MEM IMME -> MEM IMME
  75. MOV I, {src} -> 0b100 @ 0b100 @ 0b01 @ src[7:0] @ 0x00[7:0]
  76. LD I, {src} -> 0b100 @ 0b100 @ 0b01 @ src[7:0] @ 0x00[7:0]
  77.  
  78. ; MEM IMME -> MEM ADDR
  79. MOV ({dest}), {src} -> 0b101 @ 0b100 @ 0b01 @ src[7:0] @ dest[15:0]
  80. LD ({dest}), {src} -> 0b101 @ 0b100 @ 0b01 @ src[7:0] @ dest[15:0]
  81.  
  82. ; MEM IMME -> MEM ADDR CD
  83. MOV (CD), {src} -> 0b110 @ 0b100 @ 0b01 @ src[7:0]
  84. LD (CD), {src} -> 0b110 @ 0b100 @ 0b01 @ src[7:0]
  85.  
  86. ; MEM IMME -> MEM ADDR CDB
  87. MOV (CDB), {src} -> 0b111 @ 0b100 @ 0b01 @ src[7:0]
  88. LD (CDB), {src} -> 0b111 @ 0b100 @ 0b01 @ src[7:0]
  89.  
  90. ;------------------------------------------------------------------------------------------
  91. ; MEM ADDR -> REG
  92. MOV {dest: REG}, ({src}) -> dest[2:0] @ 0b101 @ 0b01 @ src[15:0]
  93. LD {dest: REG}, ({src}) -> dest[2:0] @ 0b101 @ 0b01 @ src[15:0]
  94.  
  95. ; MEM ADDR -> MEM IMME
  96. MOV I, ({src}) -> 0b100 @ 0b101 @ 0b01 @ src[15:0] @ 0x00[7:0]
  97. LD I, ({src}) -> 0b100 @ 0b101 @ 0b01 @ src[15:0] @ 0x00[7:0]
  98.  
  99. ; MEM ADDR -> MEM ADDR
  100. MOV ({dest}), ({src}) -> 0b101 @ 0b101 @ 0b01 @ src[15:0] @ dest[15:0]
  101. LD ({dest}), ({src}) -> 0b101 @ 0b101 @ 0b01 @ src[15:0] @ dest[15:0]
  102.  
  103. ; MEM ADDR -> MEM ADDR CD
  104. MOV (CD), ({src}) -> 0b110 @ 0b101 @ 0b01 @ src[15:0] @ dest[15:0]
  105. LD (CD), ({src}) -> 0b110 @ 0b101 @ 0b01 @ src[15:0] @ dest[15:0]
  106.  
  107. ; MEM ADDR -> MEM ADDR CDB
  108. MOV (CDB), ({src}) -> 0b111 @ 0b101 @ 0b01 @ src[15:0] @ dest[15:0]
  109. LD (CDB), ({src}) -> 0b111 @ 0b101 @ 0b01 @ src[15:0] @ dest[15:0]
  110.  
  111. ;------------------------------------------------------------------------------------------
  112. ; MEM ADDR CD -> REG
  113. MOV {dest: REG}, (CD) -> dest[2:0] @ 0b110 @ 0b01
  114. LD {dest: REG}, (CD) -> dest[2:0] @ 0b110 @ 0b01
  115.  
  116. ; MEM ADDR CD -> MEM IMME
  117. MOV I, (CD) -> 0b100 @ 0b110 @ 0b01 @ 0x00[7:0]
  118. LD I, (CD) -> 0b100 @ 0b110 @ 0b01 @ 0x00[7:0]
  119.  
  120. ; MEM ADDR CD -> MEM ADDR
  121. MOV {dest}, (CD) -> 0b101 @ 0b110 @ 0b01 @ dest[15:0]
  122. LD {dest}, (CD) -> 0b101 @ 0b110 @ 0b01 @ dest[15:0]
  123.  
  124. ; MEM ADDR CD -> MEM ADDR CD
  125. MOV (CD), (CD) -> 0b110 @ 0b110 @ 0b01
  126. LD (CD), (CD) -> 0b110 @ 0b110 @ 0b01
  127.  
  128. ; MEM ADDR CD -> MEM ADDR CDB
  129. MOV (CDB), (CD) -> 0b111 @ 0b110 @ 0b01
  130. LD (CDB), (CD) -> 0b111 @ 0b110 @ 0b01
  131.  
  132. ;------------------------------------------------------------------------------------------
  133. ; MEM ADDR CDB -> REG
  134. MOV {dest: REG}, (CDB) -> dest[2:0] @ 0b111 @ 0b01
  135. LD {dest: REG}, (CDB) -> dest[2:0] @ 0b111 @ 0b01
  136.  
  137. ; MEM ADDR CDB -> MEM IMME
  138. MOV I, (CDB) -> 0b100 @ 0b111 @ 0b01 @ 0x00[7:0]
  139. LD I, (CDB) -> 0b100 @ 0b111 @ 0b01 @ 0x00[7:0]
  140.  
  141. ; MEM ADDR CDB -> MEM ADDR
  142. MOV {dest}, (CDB) -> 0b101 @ 0b111 @ 0b01 @ dest[15:0]
  143. LD {dest}, (CDB) -> 0b101 @ 0b111 @ 0b01 @ dest[15:0]
  144.  
  145. ; MEM ADDR CDB -> MEM ADDR CD
  146. MOV (CD), (CDB) -> 0b110 @ 0b111 @ 0b01
  147. LD (CD), (CDB) -> 0b110 @ 0b111 @ 0b01
  148.  
  149. ; MEM ADDR CDB -> MEM ADDR CDB
  150. MOV (CDB), (CDB) -> 0b111 @ 0b111 @ 0b01
  151. LD (CDB), (CDB) -> 0b111 @ 0b111 @ 0b01
  152.  
  153. ;------------------------------------------------------------------------------------------
  154. ;------------------------------------------------------------------------------------------
  155. ; ALI - REG
  156. {al: ALS} {src: REG} -> al[2:0] @ src[2:0] @ 0b10
  157.  
  158. ;------------------------------------------------------------------------------------------
  159. ; ALI - MEM IMME
  160. {al: ALS} {src} -> al[2:0] @ 0b100 @ 0b10 @ src[7:0]
  161.  
  162. ;------------------------------------------------------------------------------------------
  163. ; ALI - MEM ADDR
  164. {al: ALS} ({src}) -> al[2:0] @ 0b101 @ 0b10 @ src[15:0]
  165.  
  166. ;------------------------------------------------------------------------------------------
  167. ; ALI - MEM ADDR CD
  168. {al: ALS} (CD) -> al[2:0] @ 0b110 @ 0b10
  169.  
  170. ;------------------------------------------------------------------------------------------
  171. ; ALI - MEM ADDR CDB
  172. {al: ALS} (CDB) -> al[2:0] @ 0b111 @ 0b10
  173.  
  174. ;------------------------------------------------------------------------------------------
  175. ;------------------------------------------------------------------------------------------
  176. ; JMP Relative
  177. JPR A -> 0b000 @ 0b000 @ 0b11
  178. JR A -> 0b000 @ 0b000 @ 0b11
  179. JPR B -> 0b000 @ 0b001 @ 0b11
  180. JR B -> 0b000 @ 0b001 @ 0b11
  181. JPR CD -> 0b000 @ 0b010 @ 0b11
  182. JR CD -> 0b000 @ 0b010 @ 0b11
  183.  
  184. ;------------------------------------------------------------------------------------------
  185. ; JMP Normal
  186. JMP CD -> 0b000 @ 0b011 @ 0b11
  187. JP CD -> 0b000 @ 0b011 @ 0b11
  188. JMP CDB -> 0b000 @ 0b100 @ 0b11
  189. JP CDB -> 0b000 @ 0b100 @ 0b11
  190. JMP {src} -> 0b000 @ 0b101 @ 0b11 @ src[15:0]
  191. JP {src} -> 0b000 @ 0b101 @ 0b11 @ src[15:0]
  192.  
  193. ;------------------------------------------------------------------------------------------
  194. ; JMP Address
  195. JMP (CD) -> 0b000 @ 0b110 @ 0b11
  196. JP (CD) -> 0b000 @ 0b110 @ 0b11
  197. JMP (CDB) -> 0b000 @ 0b111 @ 0b11
  198. JP (CDB) -> 0b000 @ 0b111 @ 0b11
  199.  
  200. ;------------------------------------------------------------------------------------------
  201. ;------------------------------------------------------------------------------------------
  202. ; JMP Relative Conditional
  203. JPR{fl: FLAGS} A -> 0b100 @ 0b000 @ 0b11 @ fl[7:0]
  204. JR{fl: FLAGS} A -> 0b100 @ 0b000 @ 0b11 @ fl[7:0]
  205. JPR{fl: FLAGS} B -> 0b100 @ 0b001 @ 0b11 @ fl[7:0]
  206. JR{fl: FLAGS} B -> 0b100 @ 0b001 @ 0b11 @ fl[7:0]
  207. JPR{fl: FLAGS} CD -> 0b100 @ 0b010 @ 0b11 @ fl[7:0]
  208. JR{fl: FLAGS} CD -> 0b100 @ 0b010 @ 0b11 @ fl[7:0]
  209.  
  210. ;------------------------------------------------------------------------------------------
  211. ; JMP Normal Conditional
  212. JMP{fl: FLAGS} CD -> 0b100 @ 0b011 @ 0b11 @ fl[7:0]
  213. JP{fl: FLAGS} CD -> 0b100 @ 0b011 @ 0b11 @ fl[7:0]
  214. JMP{fl: FLAGS} CDB -> 0b100 @ 0b100 @ 0b11 @ fl[7:0]
  215. JP{fl: FLAGS} CDB -> 0b100 @ 0b100 @ 0b11 @ fl[7:0]
  216. JMP{fl: FLAGS} {src} -> 0b100 @ 0b101 @ 0b11 @ src[15:0] @ fl[7:0]
  217. JP{fl: FLAGS} {src} -> 0b100 @ 0b101 @ 0b11 @ src[15:0] @ fl[7:0]
  218.  
  219. ;------------------------------------------------------------------------------------------
  220. ; JMP Address Conditional
  221. JMP{fl: FLAGS} (CD) -> 0b100 @ 0b110 @ 0b11 @ fl[7:0]
  222. JP{fl: FLAGS} (CD) -> 0b100 @ 0b110 @ 0b11 @ fl[7:0]
  223. JMP{fl: FLAGS} (CDB) -> 0b100 @ 0b111 @ 0b11 @ fl[7:0]
  224. JP{fl: FLAGS} (CDB) -> 0b100 @ 0b111 @ 0b11 @ fl[7:0]
  225.  
  226. ;------------------------------------------------------------------------------------------
  227. ;------------------------------------------------------------------------------------------
  228. ; CALL Relative
  229. CALLR A -> 0b000 @ 0b000 @ 0b11
  230. CLR A -> 0b000 @ 0b000 @ 0b11
  231. CALLR B -> 0b000 @ 0b001 @ 0b11
  232. CLR B -> 0b000 @ 0b001 @ 0b11
  233. CALLR CD -> 0b000 @ 0b010 @ 0b11
  234. CLR CD -> 0b000 @ 0b010 @ 0b11
  235.  
  236. ;------------------------------------------------------------------------------------------
  237. ; CALL Normal
  238. CALL CD -> 0b000 @ 0b011 @ 0b11
  239. CL CD -> 0b000 @ 0b011 @ 0b11
  240. CALL CDB -> 0b000 @ 0b100 @ 0b11
  241. CL CDB -> 0b000 @ 0b100 @ 0b11
  242. CALL {src} -> 0b000 @ 0b101 @ 0b11 @ src[15:0]
  243. CL {src} -> 0b000 @ 0b101 @ 0b11 @ src[15:0]
  244.  
  245. ;------------------------------------------------------------------------------------------
  246. ; CALL Address
  247. CALL (CD) -> 0b000 @ 0b110 @ 0b11
  248. CL (CD) -> 0b000 @ 0b110 @ 0b11
  249. CALL (CDB) -> 0b000 @ 0b111 @ 0b11
  250. CL (CDB) -> 0b000 @ 0b111 @ 0b11
  251.  
  252. ;------------------------------------------------------------------------------------------
  253. ;------------------------------------------------------------------------------------------
  254. ; CALL Relative Conditional
  255. CALLR{fl: FLAGS} A -> 0b000 @ 0b000 @ 0b11 @ fl[7:0]
  256. CLR{fl: FLAGS} A -> 0b000 @ 0b000 @ 0b11 @ fl[7:0]
  257. CALLR{fl: FLAGS} B -> 0b000 @ 0b001 @ 0b11 @ fl[7:0]
  258. CLR{fl: FLAGS} B -> 0b000 @ 0b001 @ 0b11 @ fl[7:0]
  259. CALLR{fl: FLAGS} CD -> 0b000 @ 0b010 @ 0b11 @ fl[7:0]
  260. CLR{fl: FLAGS} CD -> 0b000 @ 0b010 @ 0b11 @ fl[7:0]
  261.  
  262. ;------------------------------------------------------------------------------------------
  263. ; CALL Normal Conditional
  264. CALL{fl: FLAGS} CD -> 0b000 @ 0b011 @ 0b11 @ fl[7:0]
  265. CL{fl: FLAGS} CD -> 0b000 @ 0b011 @ 0b11 @ fl[7:0]
  266. CALL{fl: FLAGS} CDB -> 0b000 @ 0b100 @ 0b11 @ fl[7:0]
  267. CL{fl: FLAGS} CDB -> 0b000 @ 0b100 @ 0b11 @ fl[7:0]
  268. CALL{fl: FLAGS} {src} -> 0b000 @ 0b101 @ 0b11 @ src[15:0] @ fl[7:0]
  269. CL{fl: FLAGS} {src} -> 0b000 @ 0b101 @ 0b11 @ src[15:0] @ fl[7:0]
  270.  
  271. ;------------------------------------------------------------------------------------------
  272. ; CALL Address Conditional
  273. CALL{fl: FLAGS} (CD) -> 0b000 @ 0b110 @ 0b11 @ fl[7:0]
  274. CL{fl: FLAGS} (CD) -> 0b000 @ 0b110 @ 0b11 @ fl[7:0]
  275. CALL{fl: FLAGS} (CDB) -> 0b000 @ 0b111 @ 0b11 @ fl[7:0]
  276. CL{fl: FLAGS} (CDB) -> 0b000 @ 0b111 @ 0b11 @ fl[7:0]
  277.  
  278. ;------------------------------------------------------------------------------------------
  279. ;------------------------------------------------------------------------------------------
  280. }
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