`timescale 1ns / 1ps
module func_dc(
	input[0:4] in,
	output f
);
	wire[4:0] w01, w02;
	wire[4:0] w1,w3, w4, w5, w7, w8;
	dc #(2) dc10(.Ena(~in[0]), .a({in[1], in[2]}), .Y(w01));
	dc #(2) dc11(.Ena(in[0]), .a({in[1], in[2]}), .Y(w02));

	dc #(2) dc20(.Ena(w01[0] || w01[1]), .a({in[3], in[4]}), .Y(w1));
	dc #(2) dc21(.Ena(w01[2]), .a({in[3], in[4]}), .Y(w3));
	dc #(2) dc23(.Ena(w01[3]), .a({in[3], in[4]}), .Y(w4));
	dc #(2) dc24(.Ena(w02[0] || w02[1]), .a({in[3], in[4]}), .Y(w5));
	dc #(2) dc26(.Ena(w02[2]), .a({in[3], in[4]}), .Y(w7));
	dc #(2) dc27(.Ena(w02[3]), .a({in[3], in[4]}), .Y(w8));


assign f = w1[2]| w1[3]
| w3[1] | w3[2]
| w4[1] | w4[2] | w4[3]
| w5[0]
| w7[0] | w7[3]
| w8[0] | w8[2];
endmodule