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vim3 lab hdmi minihd

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  1. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;0.
  2. bl2_stage_init 0x01
  3. bl2_stage_init 0x81
  4. hw id: 0x0000 - pwm id 0x01
  5. bl2_stage_init 0xc1
  6. bl2_stage_init 0x02
  7.  
  8. L0:00000000
  9. L1:20000703
  10. L2:00008067
  11. L3:14000000
  12. B2:00402000
  13. B1:e0f83180
  14.  
  15. TE: 181650
  16.  
  17. BL2 Built : 19:22:01, Jul 31 2019. g12b ge9a9000 - zhiguang.ouyang@droid07-sz
  18.  
  19. Board ID = 8
  20. Set A53 clk to 24M
  21. Set A73 clk to 24M
  22. Set clk81 to 24M
  23. A53 clk: 1200 MHz
  24. A73 clk: 1200 MHz
  25. CLK81: 166.6M
  26. smccc: 00030f7d
  27. eMMC boot @ 0
  28. sw8 s
  29. DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Jul 31 2019 19:21:56
  30. board id: 8
  31. Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  32. fw parse done
  33. Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
  34. Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
  35. PIEI prepare done
  36. fastboot data load
  37. 00000000
  38. emmc switch 1 ok
  39. ddr saved addr:00016000
  40. Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
  41. 00000000
  42. emmc switch 0 ok
  43. fastboot data verify
  44. verify result: 265
  45. Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
  46. LPDDR4 probe
  47. ddr clk to 1608MHz
  48. Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
  49.  
  50. dmc_version 0001
  51. Check phy result
  52. INFO : End of CA training
  53. INFO : End of initialization
  54. INFO : Training has run successfully!
  55. Check phy result
  56. INFO : End of initialization
  57. INFO : End of read enable training
  58. INFO : End of fine write leveling
  59. INFO : End of Write leveling coarse delay
  60. INFO : Training has run successfully!
  61. Check phy result
  62. INFO : End of initialization
  63. INFO : End of read dq deskew training
  64. INFO : End of MPR read delay center optimization
  65. INFO : End of write delay center optimization
  66. INFO : End of read delay center optimization
  67. INFO : End of max read latency training
  68. INFO : Training has run successfully!
  69. 1D training succeed
  70. Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
  71. Check phy result
  72. INFO : End of initialization
  73. INFO : End of 2D read delay Voltage center optimization
  74. INFO : End of 2D read delay Voltage center optimization
  75. INFO : End of 2D write delay Voltage center optimization
  76. INFO : End of 2D write delay Voltage center optimization
  77. INFO : Training has run successfully!
  78.  
  79. channel==0
  80. RxClkDly_Margin_A0==97 ps 10
  81. TxDqDly_Margin_A0==106 ps 11
  82. RxClkDly_Margin_A1==87 ps 9
  83. TxDqDly_Margin_A1==106 ps 11
  84. TrainedVREFDQ_A0==26
  85. TrainedVREFDQ_A1==26
  86. VrefDac_Margin_A0==27
  87. DeviceVref_Margin_A0==26
  88. VrefDac_Margin_A1==29
  89. DeviceVref_Margin_A1==26
  90.  
  91.  
  92. channel==1
  93. RxClkDly_Margin_A0==97 ps 10
  94. TxDqDly_Margin_A0==106 ps 11
  95. RxClkDly_Margin_A1==97 ps 10
  96. TxDqDly_Margin_A1==106 ps 11
  97. TrainedVREFDQ_A0==24
  98. TrainedVREFDQ_A1==24
  99. VrefDac_Margin_A0==29
  100. DeviceVref_Margin_A0==24
  101. VrefDac_Margin_A1==28
  102. DeviceVref_Margin_A1==24
  103.  
  104. dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
  105.  
  106. soc_vref_reg_value 0x 00000029 00000026 00000029 00000027 00000027 00000027 00000027 00000025 00000027 00000027 00000024 00000026 00000027 00000027 00000026 00000026 00000027 00000029 00000028 00000029 00000028 00000028 00000028 00000027 00000029 00000027 00000028 00000027 00000029 00000027 00000029 00000027 dram_vref_reg_value 0x 00000012
  107. 2D training succeed
  108. aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Jul 31 2019 19:22:05
  109. auto size-- 65535DDR cs0 size: 2048MB
  110. DDR cs1 size: 2048MB
  111. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  112. cs0 DataBus test pass
  113. cs1 DataBus test pass
  114. cs0 AddrBus test pass
  115. cs1 AddrBus test pass
  116.  
  117. 100bdlr_step_size ps== 444
  118. result report
  119. boot times 0Enable ddr reg access
  120. 00000000
  121. emmc switch 3 ok
  122. Authentication key not yet programmed
  123. get rpmb counter error 0x00000007
  124. 00000000
  125. emmc switch 0 ok
  126. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  127. Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x000d6600, part: 0
  128. 0.0;M3 CHK:0;cm4_sp_mode 0
  129. MVN_1=0x00000000
  130. MVN_2=0x00000000
  131. [Image: g12b_v1.1.3386-3b31431 2019-05-21 10:42:10 luan.yuan@droid15-sz]
  132. OPS=0x10
  133. ring efuse init
  134. chipver efuse init
  135. 29 0b 10 00 01 05 1c 00 00 04 37 30 4e 42 4e 50
  136. [0.018961 Inits done]
  137. secure task start!
  138. high task start!
  139. low task start!
  140. run into bl31
  141. NOTICE: BL31: v1.3(release):4fc40b1
  142. NOTICE: BL31: Built : 15:58:17, May 22 2019
  143. NOTICE: BL31: G12A normal boot!
  144. NOTICE: BL31: BL33 decompress pass
  145. ERROR: Error initializing runtime service opteed_fast
  146.  
  147.  
  148. U-Boot 2015.01-g5a7732a-dirty (Aug 09 2019 - 14:42:00)
  149.  
  150. DRAM: 3.8 GiB
  151. Relocation Offset is: d6e2f000
  152. spi_post_bind(spifc): req_seq = 0
  153. register usb cfg[0][1] = 00000000d7f2f2d0
  154. aml_i2c_init_port init regs for 0
  155. NAND: get_sys_clk_rate_mtd() 270, clock setting 200!
  156. NAND device id: 0 bf ff ff ff ff
  157. No NAND device found!!!
  158. nand init failed: -6
  159. get_sys_clk_rate_mtd() 270, clock setting 200!
  160. NAND device id: 0 9f ff ff ff ff
  161. No NAND device found!!!
  162. nand init failed: -6
  163. MMC: aml_priv->desc_buf = 0x00000000d3e1fa70
  164. aml_priv->desc_buf = 0x00000000d3e21db0
  165. SDIO Port B: 0, SDIO Port C: 1
  166. co-phase 0x3, tx-dly 0, clock 400000
  167. co-phase 0x3, tx-dly 0, clock 400000
  168. co-phase 0x3, tx-dly 0, clock 400000
  169. emmc/sd response timeout, cmd8, status=0x3ff2800
  170. emmc/sd response timeout, cmd55, status=0x3ff2800
  171. co-phase 0x3, tx-dly 0, clock 400000
  172. co-phase 0x1, tx-dly 0, clock 40000000
  173. aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x2000
  174. [mmc_startup] mmc refix success
  175. init_part() 297: PART_TYPE_AML
  176. [mmc_init] mmc init success
  177. start dts,buffer=00000000d3e24620,dt_addr=00000000d3e24620
  178. get_partition_from_dts() 71: ret 0
  179. parts: 17
  180. 00: logo 0000000000800000 1
  181. 01: recovery 0000000001800000 1
  182. 02: misc 0000000000800000 1
  183. 03: dtbo 0000000000800000 1
  184. 04: cri_data 0000000000800000 2
  185. 05: param 0000000001000000 2
  186. 06: boot 0000000001000000 1
  187. set has_boot_slot = 0
  188. 07: rsv 0000000001000000 1
  189. 08: metadata 0000000001000000 1
  190. 09: vbmeta 0000000000200000 1
  191. 10: tee 0000000002000000 1
  192. 11: vendor 0000000010000000 1
  193. 12: odm 0000000008000000 1
  194. 13: system 0000000050000000 1
  195. 14: product 0000000008000000 1
  196. 15: cache 0000000046000000 2
  197. 16: data ffffffffffffffff 4
  198. init_part() 297: PART_TYPE_AML
  199. eMMC/TSD partition table have been checked OK!
  200. crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
  201. crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
  202. crc32_s:0x79f50f07 == storage crc_pattern:0x79f50f07!!!
  203. mmc env offset: 0x4d400000
  204. In: serial
  205. Out: serial
  206. Err: serial
  207. reboot_mode=cold_boot
  208. [store]To run cmd[emmc dtb_read 0x1000000 0x40000]
  209. _verify_dtb_checksum()-3406: calc ffb5c9ab, store ffb5c9ab
  210. _verify_dtb_checksum()-3406: calc ffb5c9ab, store ffb5c9ab
  211. dtb_read()-3623: total valid 2
  212. update_old_dtb()-3604: do nothing
  213. aml_i2c_init_port init regs for 0
  214. fusb302_init: Device ID: 0x91
  215. CC connected in 1 as UFP
  216. fusb302 detect chip.port_num = 0
  217. amlkey_init() enter!
  218. [EFUSE_MSG]keynum is 1
  219. vpu: clk_level in dts: 7
  220. vpu: vpu_power_on
  221. vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
  222. vpu: vpu_module_init_config
  223. vpp: vpp_init
  224. vpp: g12a/b osd1 matrix rgb2yuv ..............
  225. vpp: g12a/b osd2 matrix rgb2yuv..............
  226. vpp: g12a/b osd3 matrix rgb2yuv..............
  227. cvbs: cpuid:0x29
  228. lcd: detect mode: tablet, key_valid: 0
  229. lcd: load config from dts
  230. lcd: pinctrl_version: 2
  231. lcd: use panel_type=lcd_1
  232. lcd: bl: pinctrl_version: 2
  233. lcd: bl: name: backlight_pwm, method: 1
  234. lcd: bl: aml_bl_power_ctrl: 0
  235. Net: dwmac.ff3f0000amlkey_init() enter!
  236. amlkey_init() 71: already init!
  237. [EFUSE_MSG]keynum is 1
  238. MACADDR:02:00:00:1c:05:01(from chipid)
  239.  
  240. CONFIG_AVB2:
  241. Start read misc partition datas!
  242. info->magic =
  243. info->version_major = 1
  244. info->version_minor = 0
  245. info->slots[0].priority = 15
  246. info->slots[0].tries_remaining = 7
  247. info->slots[0].successful_boot = 0
  248. info->slots[1].priority = 14
  249. info->slots[1].tries_remaining = 7
  250. info->slots[1].successful_boot = 0
  251. info->crc32 = -1075449479
  252. active slot = 0
  253. wipe_data=successful
  254. wipe_cache=successful
  255. upgrade_step=2
  256. reboot_mode:::: cold_boot
  257.  
  258.  
  259. lcd: error: outputmode[576cvbs] is not support
  260. hpd_state=1
  261. edid preferred_mode is 1080p60hz[16]
  262. hdr mode is 0
  263. dv mode is ver:0 len: 0
  264. hdr10+ mode is 0
  265. [OSD]load fb addr from dts:/meson-fb
  266. [OSD]set initrd_high: 0x7f800000
  267. [OSD]fb_addr for logo: 0x7f800000
  268. [OSD]load fb addr from dts:/meson-fb
  269. [OSD]fb_addr for logo: 0x7f800000
  270. [OSD]VPP_OFIFO_SIZE:0xfff01fff
  271. [CANVAS]canvas init
  272. [CANVAS]addr=0x7f800000 width=3840, height=2160
  273. [OSD]osd_hw.free_dst_data: 0,1919,0,1079
  274. [OSD]osd1_update_disp_freescale_enable
  275. cvbs: outputmode[1080p60hz] is invalid
  276. vpp: vpp_matrix_update: 2
  277. set hdmitx VIC = 16
  278. config HPLL = 5940000 frac_rate = 1
  279. HPLL: 0x3b3a04f7
  280. HPLL: 0x1b3a04f7
  281. HPLLv1: 0xdb3a04f7
  282. config HPLL done
  283. j = 6 vid_clk_div = 1
  284. hdmitx phy setting done
  285. hdmitx: set enc for VIC: 16
  286. enc_vpu_bridge_reset[1235]
  287. rx version is 1.4 or below div=10
  288. vpp: sdr_mode = 2
  289. vpp: Rx hdr_info.hdr_sup_eotf_smpte_st_2084 = 0
  290. normal power on
  291. boot wol: disable
  292. saradc: 0x289, hw_ver: 0x31
  293.  
  294.  
  295. gpio: pin GPIOAO_7 (gpio 7) value is 1
  296. port mode is usb3.0
  297. Command: bcb uboot-command
  298. Start read misc partition datas!
  299. BCB hasn't any datas,exit!
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