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Lantiq xrx200 ethernet driver with SMP

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  1. --- a/drivers/net/ethernet/lantiq_xrx200.c  2019-08-13 05:00:34.508512839 +0200
  2. +++ b/drivers/net/ethernet/lantiq_xrx200.c  2019-08-12 05:24:46.769583694 +0200
  3. @@ -36,16 +36,20 @@
  4.  #include "lantiq_pce.h"
  5.  #include "lantiq_xrx200_sw.h"
  6.  
  7. -#define SW_POLLING
  8. -#define SW_ROUTING
  9. +#define SW_POLLING //polls phy
  10. +#define SW_ROUTING //adds vlan field
  11.  
  12. -#ifdef SW_ROUTING
  13. -#define XRX200_MAX_DEV     2
  14. -#else
  15. -#define XRX200_MAX_DEV     1
  16. -#endif
  17. +/* set number of TX queues: 1-2 */
  18. +#define MAX_TX_RINGS       2
  19. +
  20. +/* set number of RX queues: 1 */
  21. +#define MAX_RX_RINGS       1
  22. +
  23. +/* set number of TX queues: 1-2 */
  24. +#define MAX_TX_QUEUES      2
  25.  
  26.  #define XRX200_MAX_VLAN        64
  27. +
  28.  #define XRX200_PCE_ACTVLAN_IDX 0x01
  29.  #define XRX200_PCE_VLANMAP_IDX 0x02
  30.  
  31. @@ -54,7 +58,8 @@
  32.  
  33.  #define XRX200_HEADROOM        4
  34.  
  35. -#define XRX200_TX_TIMEOUT  (10 * HZ)
  36. +//TODO fine tune
  37. +#define XRX200_TX_TIMEOUT  (20 * HZ)
  38.  
  39.  /* port type */
  40.  #define XRX200_PORT_TYPE_PHY   1
  41. @@ -62,12 +67,14 @@
  42.  
  43.  /* DMA */
  44.  #define XRX200_DMA_DATA_LEN    0x600
  45. +#define XRX200_DMA_TX_ALIGN    (32 - 1)
  46. +
  47. +//TODO in devicetree?
  48.  #define XRX200_DMA_IRQ     INT_NUM_IM2_IRL0
  49.  #define XRX200_DMA_RX      0
  50.  #define XRX200_DMA_TX      1
  51.  #define XRX200_DMA_TX_2        3
  52. -#define XRX200_DMA_IS_TX(x)    (x%2)
  53. -#define XRX200_DMA_IS_RX(x)    (!XRX200_DMA_IS_TX(x))
  54. +// #define XRX200_DMA_TX_3     5
  55.  
  56.  /* fetch / store dma */
  57.  #define FDMA_PCTRL0        0x2A00
  58. @@ -188,12 +195,142 @@
  59.  #define MDIO_DEVAD_NONE        (-1)
  60.  #define ADVERTIZE_MPD      (1 << 10)
  61.  
  62. +//dev_set_drvdata
  63. +//https://elixir.bootlin.com/linux/v5.1-rc5/source/include/linux/device.h#L1136
  64. +//SET_NETDEV_DEV
  65. +//https://elixir.bootlin.com/linux/v5.1-rc5/source/include/linux/netdevice.h#L2208
  66. +
  67. +
  68. +// TODO interesting: save the structure at the begin of the skb - free alloc and free
  69. +/* this is used in DMA ring to match skb during cleanup */
  70. +struct xrx200_tx_skb {
  71. +   /* skb in use reference */
  72. +   struct sk_buff *skb;
  73. +
  74. +   /* tx queue reference for TX housekeeping */
  75. +   struct xrx200_tx_queue *txq;
  76. +
  77. +   /* saved dma address for unmap */
  78. +   dma_addr_t addr;
  79. +
  80. +   /* saved length for unmap, max 4096 */
  81. +   unsigned short size;
  82. +};
  83. +
  84. +
  85. +struct xrx200_rx_skb {
  86. +   /* skb in use reference */
  87. +   struct sk_buff *skb;
  88. +
  89. +   /* saved dma address for unmap */
  90. +   dma_addr_t addr;
  91. +
  92. +   /* saved length for unmap, max 4096 */
  93. +//     unsigned short size;
  94. +};
  95. +
  96. +
  97. +//mapped exactly to one ring
  98. +struct xrx200_tx_queue {
  99. +   //only one writer must be possible!!
  100. +   struct xrx200_tx_skb *skb_list; //up to ring sized number of skbs
  101. +
  102. +   //can overflow?, scheduling
  103. +   unsigned int head;  //+1 when enqueued new packet into ring
  104. +   unsigned int tail;  //+1 when cleaned
  105. +
  106. +   unsigned int num;   //queue ring size
  107. +
  108. +   struct u64_stats_sync syncp;
  109. +   __u64 tx_packets;
  110. +   __u64 tx_bytes;
  111. +   __u64 tx_errors;
  112. +   __u64 tx_dropped;
  113. +
  114. +   //associated netdev queue
  115. +   struct netdev_queue *nqueue;
  116. +
  117. +   //for the TX queue list for TX ring
  118. +   struct list_head queue; //TODO rename?
  119. +
  120. +   struct xrx200_tx_ring *ring;    //associated ring
  121. +};
  122. +
  123. +
  124. +struct xrx200_tx_ring {
  125. +   struct napi_struct napi;
  126. +
  127. +   /* ring buffer tail pointer */
  128. +   unsigned int free;
  129. +   // ____cacheline_aligned_in_smp;
  130. +
  131. +   /* user side ring for list pointers to xrx200 skb buffer */
  132. +   //NOTICE array could be directly there, it would mean:
  133. +   //  ring locking or
  134. +   //  (MAX_SKB_FRAGS+1)*sizeof(struct xrx200_skb) bytes in local variables
  135. +   //  (MAX_SKB_FRAGS+1)*sizeof(struct xrx200_skb) memcpy'd bytes
  136. +   struct xrx200_tx_skb **skb_list_ptr;
  137. +
  138. +   /* settings of this DMA ring */
  139. +   struct ltq_dma_channel dma;
  140. +
  141. +   /* number of ring members */
  142. +   //TODO this should be adjustable and in ltq_dma_channel
  143. +   int num;
  144. +
  145. +   struct xrx200_priv *priv;
  146. +
  147. +   /* sharing the ring between multiple queues */
  148. +   spinlock_t lock;
  149. +
  150. +   /* list of assigned TX queues, for IRQ */
  151. +   struct list_head queues;
  152. +};
  153. +
  154. +
  155. +//TODO is priv required in both queue and ring? probably just ring?
  156. +struct xrx200_rx_queue {
  157. +   /* netdev stats */
  158. +   struct u64_stats_sync syncp;
  159. +   __u64 rx_packets;
  160. +   __u64 rx_bytes;
  161. +   __u64 rx_dropped;
  162. +
  163. +   /* link back to priv */
  164. +   struct xrx200_priv *priv;
  165. +
  166. +   /* associated DMA ring */
  167. +   struct xrx200_rx_ring *ring;
  168. +};
  169. +
  170. +
  171. +struct xrx200_rx_ring {
  172. +   /* one napi for ring */
  173. +   struct napi_struct napi;
  174. +
  175. +   /* associated DMA descriptors */
  176. +   struct ltq_dma_channel dma;
  177. +
  178. +   /* link back to priv */
  179. +   struct xrx200_priv *priv;
  180. +
  181. +   //TODO these two should be inside ltq_dma_channel
  182. +   /* additional data per DMA descriptor */
  183. +   struct xrx200_rx_skb *skb_list;
  184. +
  185. +   /* number of descriptors */
  186. +   int num;
  187. +};
  188. +
  189. +
  190.  struct xrx200_port {
  191.     u8 num;
  192.     u8 phy_addr;
  193.     u16 flags;
  194.     phy_interface_t phy_if;
  195.  
  196. +   struct list_head port;
  197. +
  198.     int link;
  199.     int gpio;
  200.     enum of_gpio_flags gpio_flags;
  201. @@ -202,53 +339,86 @@
  202.     struct device_node *phy_node;
  203.  };
  204.  
  205. -struct xrx200_chan {
  206. -   int idx;
  207. -   int refcount;
  208. -   int tx_free;
  209.  
  210. -   struct net_device dummy_dev;
  211. -   struct net_device *devs[XRX200_MAX_DEV];
  212. +#define IF_TYPE_SWITCH     0
  213. +#define IF_TYPE_WAN        1
  214.  
  215. -   struct tasklet_struct tasklet;
  216. -   struct napi_struct napi;
  217. -   struct ltq_dma_channel dma;
  218. -   struct sk_buff *skb[LTQ_DESC_NUM];
  219. +//TODO sort by sizes at the end
  220. +struct xrx200_iface {
  221. +   /* associated netdev */
  222. +   struct net_device *net_dev; //TODO zero alloc, pak se da iterovat?
  223.  
  224. -   spinlock_t lock;
  225. +   /* TX queue, sw frontend for DMA ring */
  226. +   struct xrx200_tx_queue *txq;
  227. +
  228. +   /* number of txq members */
  229. +   unsigned int num_tx_queues;
  230. +
  231. +   /* RX queue, sw frontend for shared DMA ring */
  232. +   /* NOTICE hardcoded 1 queue, because only 1 RX ring */
  233. +   struct xrx200_rx_queue *rxq;
  234. +
  235. +   /* interface's MAC address */
  236. +   unsigned char mac[6];
  237. +
  238. +   /* link to private */
  239. +   //TODO better way?
  240. +   struct xrx200_priv *priv;
  241. +
  242. +   /* interface list member, for priv*/
  243. +   struct list_head iface;
  244. +
  245. +   /* head for port list */
  246. +   //TODO this is logical hierarchy, but everybody uses for each iface/for each port
  247. +   struct list_head ports;
  248. +
  249. +   /* the interface is switch/wan type */
  250. +   //TODO maybe enum?
  251. +   unsigned int iftype;
  252. +
  253. +   /* for interface timeouts */
  254. +   struct u64_stats_sync syncp;
  255. +   __u64 tx_errors;
  256.  };
  257.  
  258. -struct xrx200_hw {
  259. +
  260. +struct xrx200_priv {
  261. +   /* for NAPI polling */
  262. +   struct net_device dummy_net;
  263. +
  264. +   /* hardware DMA ring, 2 channels for TX, FIXME if you have TRM */
  265. +   struct xrx200_tx_ring tx[MAX_TX_RINGS];
  266. +
  267. +   /* hardware DMA ring, 1 channel for RX, FIXME if you have TRM */
  268. +   struct xrx200_rx_ring rx[MAX_RX_RINGS];
  269. +
  270. +   /* head for interfaces list */
  271. +   struct list_head ifaces;
  272. +
  273.     struct clk *clk;
  274. -   struct mii_bus *mii_bus;
  275.  
  276. -   struct xrx200_chan chan[XRX200_MAX_DMA];
  277. -   u16 vlan_vid[XRX200_MAX_VLAN];
  278. -   u16 vlan_port_map[XRX200_MAX_VLAN];
  279. +   struct device *dev;
  280.  
  281. -   struct net_device *devs[XRX200_MAX_DEV];
  282. -   int num_devs;
  283. +   /* default portmap */
  284. +   //TODO only switch affected? maybe put into iface
  285. +   unsigned short d_port_map;
  286.  
  287. -   int port_map[XRX200_MAX_PORT];
  288. +   //TODO seems wan map can be only at MII-1
  289. +   /* wan port map, maybe equivalent to d_port_map? */
  290.     unsigned short wan_map;
  291.  
  292. -   struct switch_dev swdev;
  293. -};
  294. +   u16 vlan_vid[XRX200_MAX_VLAN];
  295. +   u16 vlan_port_map[XRX200_MAX_VLAN];
  296.  
  297. -struct xrx200_priv {
  298. -   struct net_device_stats stats;
  299. -   int id;
  300. +   /* RX: MII port to interface mapping */
  301. +   struct xrx200_iface *port_map[XRX200_MAX_PORT];
  302.  
  303. -   struct xrx200_port port[XRX200_MAX_PORT];
  304. -   int num_port;
  305. -   bool wan;
  306. -   bool sw;
  307. -   unsigned short port_map;
  308. -   unsigned char mac[6];
  309. +   struct mii_bus *mii_bus;
  310.  
  311. -   struct xrx200_hw *hw;
  312. +   struct switch_dev swdev;
  313.  };
  314.  
  315. +
  316.  static __iomem void *xrx200_switch_membase;
  317.  static __iomem void *xrx200_mii_membase;
  318.  static __iomem void *xrx200_mdio_membase;
  319. @@ -470,14 +640,14 @@
  320.  }
  321.  
  322.  // swconfig interface
  323. -static void xrx200_hw_init(struct xrx200_hw *hw);
  324. +static void xrx200_hw_init(struct xrx200_priv *priv);
  325.  
  326.  // global
  327.  static int xrx200sw_reset_switch(struct switch_dev *dev)
  328.  {
  329. -   struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
  330. +   struct xrx200_priv *priv = container_of(dev, struct xrx200_priv, swdev);
  331.  
  332. -   xrx200_hw_init(hw);
  333. +   xrx200_hw_init(priv);
  334.  
  335.     return 0;
  336.  }
  337. @@ -523,7 +693,7 @@
  338.  static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr,
  339.                  struct switch_val *val)
  340.  {
  341. -   struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
  342. +   struct xrx200_priv *priv = container_of(dev, struct xrx200_priv, swdev);
  343.     int i;
  344.     struct xrx200_pce_table_entry tev;
  345.     struct xrx200_pce_table_entry tem;
  346. @@ -538,7 +708,7 @@
  347.             return -EINVAL;
  348.     }
  349.  
  350. -   hw->vlan_vid[val->port_vlan] = val->value.i;
  351. +   priv->vlan_vid[val->port_vlan] = val->value.i;
  352.  
  353.     tev.index = val->port_vlan;
  354.     xrx200_pce_table_entry_read(&tev);
  355. @@ -571,7 +741,7 @@
  356.  
  357.  static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
  358.  {
  359. -   struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
  360. +   struct xrx200_priv *priv = container_of(dev, struct xrx200_priv, swdev);
  361.     int i, portmap, tagmap, untagged;
  362.     struct xrx200_pce_table_entry tem;
  363.  
  364. @@ -624,7 +794,7 @@
  365.  
  366.     ltq_switch_w32_mask(0, portmap, PCE_PMAP2);
  367.     ltq_switch_w32_mask(0, portmap, PCE_PMAP3);
  368. -   hw->vlan_port_map[val->port_vlan] = portmap;
  369. +   priv->vlan_port_map[val->port_vlan] = portmap;
  370.  
  371.     xrx200sw_fixup_pvids();
  372.  
  373. @@ -722,8 +892,8 @@
  374.  
  375.     link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port);
  376.  
  377. -   link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010);
  378. -   link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020);
  379. +   link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) & 0x0010);
  380. +   link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) & 0x0020);
  381.     link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port));
  382.  
  383.     link->speed = SWITCH_PORT_SPEED_10;
  384. @@ -834,254 +1004,510 @@
  385.  // .get_port_stats = xrx200sw_get_port_stats, //TODO
  386.  };
  387.  
  388. -static int xrx200sw_init(struct xrx200_hw *hw)
  389. +static int xrx200sw_init(struct xrx200_iface *iface)
  390.  {
  391. -   int netdev_num;
  392.  
  393. -   for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++)
  394. -   {
  395. -       struct switch_dev *swdev;
  396. -       struct net_device *dev = hw->devs[netdev_num];
  397. -       struct xrx200_priv *priv = netdev_priv(dev);
  398. -       if (!priv->sw)
  399. -           continue;
  400. +   struct switch_dev *swdev;
  401. +
  402. +   //TODO is it possible to have working eth without switch? (only wan?)
  403. +   //TODO put into interface init under switch block
  404. +
  405. +   swdev = &iface->priv->swdev;
  406.  
  407. -       swdev = &hw->swdev;
  408. +   swdev->name = "Lantiq XRX200 Switch";
  409. +   swdev->vlans = XRX200_MAX_VLAN;
  410. +   swdev->ports = XRX200_MAX_PORT;
  411. +   swdev->cpu_port = 6;
  412. +   swdev->ops = &xrx200sw_ops;
  413.  
  414. -       swdev->name = "Lantiq XRX200 Switch";
  415. -       swdev->vlans = XRX200_MAX_VLAN;
  416. -       swdev->ports = XRX200_MAX_PORT;
  417. -       swdev->cpu_port = 6;
  418. -       swdev->ops = &xrx200sw_ops;
  419. +   //TODO there should be retval?
  420. +   return register_switch(swdev, iface->net_dev);
  421. +}
  422. +
  423. +/* drop all the packets from the DMA ring */
  424. +static void xrx200_flush_rx(struct xrx200_rx_ring *ring)
  425. +{
  426. +   int i;
  427. +
  428. +   for (i = 0; i < ring->num; i++) {
  429. +       struct ltq_dma_desc *desc = &ring->dma.desc_base[ring->dma.desc];
  430. +
  431. +       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
  432. +           break;
  433. +
  434. +       desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
  435. +               XRX200_DMA_DATA_LEN;
  436.  
  437. -       register_switch(swdev, dev);
  438. -       return 0; // enough switches
  439. +       ring->dma.desc = (ring->dma.desc + 1) % ring->num;
  440.     }
  441. -   return 0;
  442.  }
  443.  
  444. +
  445.  static int xrx200_open(struct net_device *dev)
  446.  {
  447. -   struct xrx200_priv *priv = netdev_priv(dev);
  448. +   struct xrx200_iface *iface = netdev_priv(dev);
  449. +   struct list_head *pos;
  450.     int i;
  451.  
  452. -   for (i = 0; i < XRX200_MAX_DMA; i++) {
  453. -       if (!priv->hw->chan[i].dma.irq)
  454. -           continue;
  455. -       spin_lock_bh(&priv->hw->chan[i].lock);
  456. -       if (!priv->hw->chan[i].refcount) {
  457. -           if (XRX200_DMA_IS_RX(i))
  458. -               napi_enable(&priv->hw->chan[i].napi);
  459. -           ltq_dma_open(&priv->hw->chan[i].dma);
  460. -       }
  461. -       priv->hw->chan[i].refcount++;
  462. -       spin_unlock_bh(&priv->hw->chan[i].lock);
  463. -   }
  464. -   for (i = 0; i < priv->num_port; i++)
  465. -       if (priv->port[i].phydev)
  466. -           phy_start(priv->port[i].phydev);
  467. -   netif_wake_queue(dev);
  468. +   for (i = 0; i < iface->num_tx_queues; i++) {
  469. +       //TODO must be locked
  470. +
  471. +       napi_enable(&iface->txq[i].ring->napi);
  472. +       ltq_dma_open(&iface->txq[i].ring->dma);
  473. +       ltq_dma_enable_irq(&iface->txq[i].ring->dma);
  474. +   }
  475. +
  476. +   //TODO must be locked, tx_open?
  477. +   napi_enable(&iface->rxq[0].ring->napi);
  478. +   ltq_dma_open(&iface->rxq[0].ring->dma);
  479. +
  480. +   /* The boot loader does not always deactivate the receiving of frames
  481. +    * on the ports and then some packets queue up in the PPE buffers.
  482. +    * They already passed the PMAC so they do not have the tags
  483. +    * configured here. Read the these packets here and drop them.
  484. +    * The HW should have written them into memory after 10us
  485. +    */
  486. +   usleep_range(20, 40);
  487. +   xrx200_flush_rx(iface->rxq[0].ring);
  488. +
  489. +   ltq_dma_enable_irq(&iface->rxq[0].ring->dma);
  490. +
  491. +   list_for_each(pos, &iface->ports) {
  492. +       struct xrx200_port *port = list_entry(pos,
  493. +                             struct xrx200_port,
  494. +                             port);
  495. +       if (port->phydev)
  496. +           phy_start(port->phydev);
  497. +   }
  498. +
  499. +   netif_tx_wake_all_queues(dev);
  500.  
  501.     return 0;
  502.  }
  503.  
  504.  static int xrx200_close(struct net_device *dev)
  505.  {
  506. -   struct xrx200_priv *priv = netdev_priv(dev);
  507. +   struct xrx200_iface *iface = netdev_priv(dev);
  508. +   struct list_head *pos;
  509.     int i;
  510.  
  511. -   netif_stop_queue(dev);
  512. +   netif_tx_stop_all_queues(dev);
  513.  
  514. -   for (i = 0; i < priv->num_port; i++)
  515. -       if (priv->port[i].phydev)
  516. -           phy_stop(priv->port[i].phydev);
  517. +   list_for_each(pos, &iface->ports) {
  518. +       struct xrx200_port *port = list_entry(pos,
  519. +                             struct xrx200_port,
  520. +                             port);
  521. +       if (port->phydev)
  522. +           phy_stop(port->phydev);
  523. +   }
  524.  
  525. -   for (i = 0; i < XRX200_MAX_DMA; i++) {
  526. -       if (!priv->hw->chan[i].dma.irq)
  527. -           continue;
  528. +   napi_disable(&iface->rxq[0].ring->napi);
  529. +   ltq_dma_close(&iface->rxq[0].ring->dma);
  530.  
  531. -       priv->hw->chan[i].refcount--;
  532. -       if (!priv->hw->chan[i].refcount) {
  533. -           if (XRX200_DMA_IS_RX(i))
  534. -               napi_disable(&priv->hw->chan[i].napi);
  535. -           spin_lock_bh(&priv->hw->chan[i].lock);
  536. -           ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
  537. -           spin_unlock_bh(&priv->hw->chan[i].lock);
  538. -       }
  539. +   for (i = 0; i < iface->num_tx_queues; i++) {
  540. +       napi_disable(&iface->txq[i].ring->napi);
  541. +       ltq_dma_close(&iface->txq[i].ring->dma);
  542.     }
  543.  
  544.     return 0;
  545.  }
  546.  
  547. -static int xrx200_alloc_skb(struct xrx200_chan *ch)
  548. +//TODO maybe change priv to ring, alloc to RX?
  549. +static int xrx200_alloc_skb(struct xrx200_priv *priv,
  550. +               struct ltq_dma_channel *dma,
  551. +               struct xrx200_rx_skb *dma_skb)
  552.  {
  553. -#define DMA_PAD    (NET_IP_ALIGN + NET_SKB_PAD)
  554. -   ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD);
  555. -   if (!ch->skb[ch->dma.desc])
  556. +   struct ltq_dma_desc *base = &dma->desc_base[dma->desc];
  557. +   struct sk_buff *skb;
  558. +
  559. +//#define DMA_PAD  (NET_IP_ALIGN + NET_SKB_PAD)
  560. +//     skb = netdev_alloc_skb(priv->net_dev, XRX200_DMA_DATA_LEN + DMA_PAD);
  561. +
  562. +   skb = napi_alloc_skb(&priv->rx[0].napi, XRX200_DMA_DATA_LEN);
  563. +
  564. +   //TODO fix fail path
  565. +   if (unlikely(!skb)) {
  566. +       /* leave the old skb if not enough memory */
  567.         goto skip;
  568. +   }
  569. +
  570. +   if (likely(dma_skb->addr)) {
  571. +       dma_unmap_single(priv->dev, dma_skb->addr,
  572. +                XRX200_DMA_DATA_LEN, DMA_FROM_DEVICE);
  573. +   }
  574. +
  575. +   //  skb_reserve(skb, NET_SKB_PAD);
  576. +   skb_reserve(skb, -NET_IP_ALIGN);
  577. +
  578. +   base->addr = dma_skb->addr =
  579. +       dma_map_single(priv->dev, skb->data,
  580. +                  XRX200_DMA_DATA_LEN, DMA_FROM_DEVICE);
  581. +
  582. +//TODO error path
  583. +//         if (dma_mapping_error(&cp->pdev->dev, new_mapping)) {
  584. +//             dev->stats.rx_dropped++;
  585. +//             kfree_skb(new_skb);
  586. +//             goto rx_next;
  587. +//         }
  588.  
  589. -   skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD);
  590. -   ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(ch->dma.dev,
  591. -       ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
  592. -           DMA_FROM_DEVICE);
  593. -   ch->dma.desc_base[ch->dma.desc].addr =
  594. -       CPHYSADDR(ch->skb[ch->dma.desc]->data);
  595. -   skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
  596. +
  597. +   skb_reserve(skb, NET_IP_ALIGN);
  598. +
  599. +   dma_skb->skb = skb;
  600. +
  601. +   wmb();
  602.  
  603.  skip:
  604. -   ch->dma.desc_base[ch->dma.desc].ctl =
  605. -       LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
  606. +   base->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
  607.         XRX200_DMA_DATA_LEN;
  608.  
  609. +   dma->desc = (dma->desc + 1) % priv->rx[0].num;
  610. +
  611.     return 0;
  612.  }
  613.  
  614. -static void xrx200_hw_receive(struct xrx200_chan *ch, int id)
  615. +
  616. +static void xrx200_hw_receive(struct xrx200_priv *priv,
  617. +                 struct xrx200_iface *iface,
  618. +                 struct ltq_dma_channel *dma,
  619. +                 struct xrx200_rx_skb *dma_skb
  620. +                 )
  621.  {
  622. -   struct net_device *dev = ch->devs[id];
  623. -   struct xrx200_priv *priv = netdev_priv(dev);
  624. -   struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
  625. -   struct sk_buff *skb = ch->skb[ch->dma.desc];
  626. +   struct ltq_dma_desc *desc = &dma->desc_base[dma->desc];
  627. +   struct net_device *dev = iface->net_dev;
  628. +   struct xrx200_rx_queue *rxq = iface->rxq;
  629.     int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
  630.     int ret;
  631. +   /* struct value will get overwritten by xrx200_alloc_skb */
  632. +   struct sk_buff *filled_skb = dma_skb->skb;
  633.  
  634. -   ret = xrx200_alloc_skb(ch);
  635. -
  636. -   ch->dma.desc++;
  637. -   ch->dma.desc %= LTQ_DESC_NUM;
  638. +   /* alloc new skb first so DMA ring can work during netif_receive_skb */
  639. +   ret = xrx200_alloc_skb(priv, dma, dma_skb);
  640.  
  641.     if (ret) {
  642.         netdev_err(dev,
  643.             "failed to allocate new rx buffer\n");
  644. +
  645. +       //TODO
  646.         return;
  647.     }
  648.  
  649. -   skb_put(skb, len);
  650. +   /* set skb length for netdev */
  651. +   skb_put(filled_skb, len);
  652.  #ifdef SW_ROUTING
  653. -   skb_pull(skb, 8);
  654. +   /* remove special tag */
  655. +   skb_pull(filled_skb, 8);
  656.  #endif
  657. -   skb->dev = dev;
  658. -   skb->protocol = eth_type_trans(skb, dev);
  659. -   netif_receive_skb(skb);
  660. -   priv->stats.rx_packets++;
  661. -   priv->stats.rx_bytes+=len;
  662. +
  663. +   filled_skb->protocol = eth_type_trans(filled_skb, dev);
  664. +
  665. +   //TODO redo for netif_receive_skb_list? problem is deciding overhead between netdev
  666. +   ret = netif_receive_skb(filled_skb);
  667. +
  668. +   if (likely(ret == NET_RX_SUCCESS)) {
  669. +       u64_stats_update_begin(&rxq->syncp);
  670. +       rxq->rx_bytes += len;
  671. +       rxq->rx_packets++;
  672. +       u64_stats_update_end(&rxq->syncp);
  673. +   } else {
  674. +
  675. +       u64_stats_update_begin(&rxq->syncp);
  676. +       rxq->rx_dropped++;
  677. +       u64_stats_update_end(&rxq->syncp);
  678. +   }
  679. +
  680. +// info napi_gro_receive(&rxq->napi, filled_skb); too simple soc?
  681. +
  682.  }
  683.  
  684.  static int xrx200_poll_rx(struct napi_struct *napi, int budget)
  685.  {
  686. -   struct xrx200_chan *ch = container_of(napi,
  687. -               struct xrx200_chan, napi);
  688. -   struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
  689. +   struct xrx200_rx_ring *ring = container_of(napi,
  690. +                         struct xrx200_rx_ring, napi);
  691. +   struct ltq_dma_channel *dma = &ring->dma;
  692. +   struct xrx200_priv *priv = ring->priv;
  693.     int rx = 0;
  694. -   int complete = 0;
  695.  
  696. -   while ((rx < budget) && !complete) {
  697. -       struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
  698. -       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
  699. +   //read the ring
  700. +   //put skb to the correct queue
  701. +   //(if all queues have more items than ring -> ring will have to wait)
  702. +   //if all queues have less items than ring -> ring may get stuck
  703. +   //TODO delete ^^
  704. +
  705. +   while (rx < budget) {
  706. +       struct ltq_dma_desc *desc = &dma->desc_base[dma->desc];
  707. +       if (likely((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C)) {
  708. +           struct xrx200_rx_skb *dma_skb = &ring->skb_list[dma->desc];
  709. +
  710. +//TODO TODO TODO
  711. +#if 0
  712. +#if 1
  713.  #ifdef SW_ROUTING
  714. -           struct sk_buff *skb = ch->skb[ch->dma.desc];
  715. -           u8 *special_tag = (u8*)skb->data;
  716. -           int port = (special_tag[7] >> SPPID_SHIFT) & SPPID_MASK;
  717. -           xrx200_hw_receive(ch, priv->hw->port_map[port]);
  718. +           const unsigned char port = (dma_skb->skb->data[7] >> SPPID_SHIFT) & SPPID_MASK;
  719. +#else
  720. +//TODO not sure if this codepath works, anyone using !SW_ROUTING here?
  721. +           const unsigned char port = 0;
  722. +#endif
  723. +#endif
  724.  #else
  725. -           xrx200_hw_receive(ch, 0);
  726. +
  727. +//TODO forced interface 0, test uninialized ifaces -> NULL pointers
  728. +const unsigned char port = 0;
  729. +#endif
  730. +
  731. +
  732. +// TODO it could be even possible to make a single eth interface for every rj45 connector, but things like mac addresses...
  733. +
  734. +#if 0
  735. +   {
  736. +       int i;
  737. +
  738. +pr_info("%px %px %px %i %i %px, dump:\n",
  739. +dma,
  740. +dma_skb,
  741. +dma_skb->skb,
  742. +dma->desc,
  743. +port,
  744. +priv->port_map[port]->net_dev);
  745. +
  746. +       for (i = 0; i < 16;i++) {
  747. +           pr_cont("%02x ", dma_skb->skb->data[i]);
  748. +           if ((i % 8) == 7)
  749. +               pr_cont("\n");
  750. +       }
  751. +       pr_cont("\n");
  752. +   }
  753.  #endif
  754. +
  755. +//port (LAN switch/wan) is mapped on xrx200_iface
  756. +           xrx200_hw_receive(priv, priv->port_map[port], dma,
  757. +                     dma_skb);
  758.             rx++;
  759.         } else {
  760. -           complete = 1;
  761. +           break;
  762.         }
  763.     }
  764.  
  765. -   if (complete || !rx) {
  766. -       napi_complete(&ch->napi);
  767. -       ltq_dma_enable_irq(&ch->dma);
  768. +   //TODO
  769. +   if (rx < budget) {
  770. +       if (napi_complete_done(napi, rx)) {
  771. +//can an unacked irq event wait here now?
  772. +           ltq_dma_enable_irq(dma);
  773. +       }
  774.     }
  775.  
  776.     return rx;
  777.  }
  778.  
  779. -static void xrx200_tx_housekeeping(unsigned long ptr)
  780. -{
  781. -   struct xrx200_chan *ch = (struct xrx200_chan *) ptr;
  782. -   int pkts = 0;
  783. -   int i;
  784. +//TODO is this macro valid?
  785. +#define TX_BUFFS_AVAIL(tail, head, num)        \
  786. +   ((tail <= head) ?           \
  787. +     tail + (num - 1) - head : \
  788. +     tail - head - 1)
  789. +
  790. +static int xrx200_tx_housekeeping(struct napi_struct *napi, int budget)
  791. +{
  792. +   struct xrx200_tx_ring *ring =
  793. +       container_of(napi, struct xrx200_tx_ring, napi);
  794. +       //  struct net_device *net_dev = txq->priv->net_dev;
  795. +   int pkts = 0;   //napi complete has int, hw will fit into usinged short
  796. +   unsigned short size = 0;
  797. +   unsigned int free;
  798. +   struct xrx200_tx_queue *txq;
  799. +   struct ltq_dma_desc *desc;
  800. +   struct list_head *pos;
  801.  
  802. -   spin_lock_bh(&ch->lock);
  803. -   ltq_dma_ack_irq(&ch->dma);
  804. -   while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
  805. -       struct sk_buff *skb = ch->skb[ch->tx_free];
  806. +   free = ring->free;  //read once? TODO
  807.  
  808. -       pkts++;
  809. -       ch->skb[ch->tx_free] = NULL;
  810. -       dev_kfree_skb(skb);
  811. -       memset(&ch->dma.desc_base[ch->tx_free], 0,
  812. -           sizeof(struct ltq_dma_desc));
  813. -       ch->tx_free++;
  814. -       ch->tx_free %= LTQ_DESC_NUM;
  815. +//TODO pkts vs frags, frags means fullness of ring, pkts means napi budget!
  816. +
  817. +   while (likely(pkts < budget)) {
  818. +       desc = &ring->dma.desc_base[free];
  819. +
  820. +       //TODO into while condition? an additional read
  821. +       //speed tests
  822. +       if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
  823. +           struct xrx200_tx_skb *dma_skb = ring->skb_list_ptr[free];
  824. +
  825. +           //all frags after SOP are from the same TXQ
  826. +           //NOTICE but frags/pkts
  827. +//             if (desc->ctl & LTQ_DMA_SOP) {
  828. +//                 txq = skb_list_ptr[free]->txq;
  829. +//                 tail = txq->tail;
  830. +//             }
  831. +
  832. +           //TODO txq operations could be speed up, between SOP and EOP
  833. +           // there must be the same txq
  834. +           // also we could accumulate stats for one txq run
  835. +
  836. +           txq = dma_skb->txq;
  837. +
  838. +           size = dma_skb->size;
  839. +
  840. +           //TODO device
  841. +           dma_unmap_single(ring->priv->dev, dma_skb->addr,
  842. +                    (size_t) size, DMA_TO_DEVICE);
  843. +
  844. +           if (desc->ctl & LTQ_DMA_EOP) {
  845. +               //TODO there could be a local variable and update it at the end
  846. +               //problem: mixed queues
  847. +               u64_stats_update_begin(&txq->syncp);
  848. +               txq->tx_packets++;
  849. +               txq->tx_bytes += size;
  850. +               u64_stats_update_end(&txq->syncp);
  851. +
  852. +               if (likely(dma_skb->skb)) {
  853. +                   //last frag
  854. +                   dev_consume_skb_irq(dma_skb->skb);
  855. +                   dma_skb->skb = NULL;    //TODO is it required?
  856. +                   pkts++;
  857. +               } else {
  858. +                   //debug?
  859. +                   dev_warn(ring->priv->dev, "TX ring skb pointer is NULL\n");
  860. +               }
  861. +           } else {
  862. +               //TODO there could be a local variable and update it at the end
  863. +               //problem: mixed queues
  864. +               u64_stats_update_begin(&txq->syncp);
  865. +               txq->tx_bytes += size;
  866. +               u64_stats_update_end(&txq->syncp);
  867. +           }
  868. +
  869. +
  870. +           txq->tail = (txq->tail + 1) % txq->num;
  871. +
  872. +           /* erase descriptor flags */
  873. +           desc->ctl = 0;
  874. +
  875. +           free = (free + 1) % ring->num;
  876. +       } else {
  877. +           break;
  878. +       }
  879.     }
  880. -   ltq_dma_enable_irq(&ch->dma);
  881. -   spin_unlock_bh(&ch->lock);
  882.  
  883. -   if (!pkts)
  884. -       return;
  885. +   ring->free = free;
  886.  
  887. -   for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++)
  888. -       netif_wake_queue(ch->devs[i]);
  889. -}
  890. +   /* test which queue housekeeping should be scheduled */
  891. +   list_for_each(pos, &ring->queues) {
  892. +       txq = list_entry(pos, struct xrx200_tx_queue, queue);
  893. +
  894. +       /* wake up queue only if there is enough space */
  895. +       if (unlikely(TX_BUFFS_AVAIL(txq->tail, txq->head, txq->num) > (MAX_SKB_FRAGS + 1))) {
  896. +           if (netif_tx_queue_stopped(txq->nqueue)) {
  897. +               netif_tx_wake_queue(txq->nqueue);
  898. +           }
  899. +       }
  900. +   }
  901.  
  902. -static struct net_device_stats *xrx200_get_stats (struct net_device *dev)
  903. -{
  904. -   struct xrx200_priv *priv = netdev_priv(dev);
  905. +   if (pkts < budget) {
  906. +       if (napi_complete_done(napi, pkts)) {
  907. +           ltq_dma_enable_irq(&ring->dma);
  908. +       }
  909. +   }
  910.  
  911. -   return &priv->stats;
  912. +   return pkts;
  913.  }
  914.  
  915. -static void xrx200_tx_timeout(struct net_device *dev)
  916. +
  917. +static void xrx200_tx_timeout(struct net_device *ndev)
  918.  {
  919. -   struct xrx200_priv *priv = netdev_priv(dev);
  920. +   struct xrx200_iface *iface = netdev_priv(ndev);
  921. +
  922. +   netdev_err(ndev, "transmit timed out!\n");
  923.  
  924. -   printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name);
  925. +   u64_stats_update_begin(&iface->syncp);
  926. +   iface->tx_errors++;
  927. +   u64_stats_update_end(&iface->syncp);
  928.  
  929. -   priv->stats.tx_errors++;
  930. -   netif_wake_queue(dev);
  931. +   netif_tx_wake_all_queues(ndev);
  932.  }
  933.  
  934. -static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
  935. -{
  936. -   struct xrx200_priv *priv = netdev_priv(dev);
  937. -   struct xrx200_chan *ch;
  938. -   struct ltq_dma_desc *desc;
  939. -   u32 byte_offset;
  940. +
  941. +#if 0
  942. +//testing "packet"
  943. +char test_packet[] = {
  944. +   0,0,0,0,    //headroom
  945. +   0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc4, 0xe9, 0x84, 0x2a, 0xbd, 0x51, 0x08, 0x06, 0x00, 0x01,
  946. +   0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0xc4, 0xe9, 0x84, 0x2a, 0xbd, 0x51, 0x0a, 0x00, 0x00, 0x50,
  947. +   0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0a, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  948. +   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
  949. +};
  950. +
  951. +long test_counter=1;
  952. +
  953. +#endif
  954. +
  955. +//TODO netdev queues, stats per queue or netdev, is xmit exclusive
  956. +// struct napi_struct  napi ____cacheline_aligned;
  957. +//https://elixir.bootlin.com/linux/v5.1-rc5/source/drivers/net/ethernet/broadcom/bcmsysport.h#L740
  958. +// struct ltq_etop_priv *priv = netdev_priv(dev);
  959. +//stats collision in housekeeping per queue/netdev/ring ?
  960. +//MAX_SKB_FRAGS
  961. +
  962. +static netdev_tx_t xrx200_start_xmit(struct sk_buff *skb,
  963. +                    struct net_device *dev)
  964. +{
  965. +   struct xrx200_iface *iface = netdev_priv(dev);
  966. +   struct xrx200_priv *priv = iface->priv;
  967. +   struct xrx200_tx_queue *txq;
  968. +   struct xrx200_tx_ring *ring;
  969. +   unsigned int ring_head;
  970. +   unsigned int head;
  971.     int ret = NETDEV_TX_OK;
  972.     int len;
  973. +   int i;
  974. +   u16 queue_id;
  975.  #ifdef SW_ROUTING
  976.     u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
  977.  #endif
  978. -   if(priv->id)
  979. -       ch = &priv->hw->chan[XRX200_DMA_TX_2];
  980. -   else
  981. -       ch = &priv->hw->chan[XRX200_DMA_TX];
  982. +   unsigned long flags;
  983. +   unsigned int idx;
  984.  
  985. -   desc = &ch->dma.desc_base[ch->dma.desc];
  986. +   //TODO will always skb queue match nqueue from txq?
  987. +   queue_id = skb_get_queue_mapping(skb);
  988. +   txq = &iface->txq[queue_id];
  989.  
  990. -   skb->dev = dev;
  991. -   len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
  992. +   if (unlikely(TX_BUFFS_AVAIL(txq->tail, txq->head, txq->num) <= (MAX_SKB_FRAGS + 1))) {
  993. +       netif_tx_stop_queue(txq->nqueue);
  994. +
  995. +       /*
  996. +        * This is usually a bug, the code must foresee this
  997. +        * at the end of this function
  998. +        */
  999. +       netdev_err(dev, "not enough space on queue %i\n", queue_id);
  1000. +
  1001. +       return NETDEV_TX_BUSY;
  1002. +   }
  1003. +
  1004. +   if (skb_put_padto(skb, ETH_ZLEN)) {
  1005. +       /* XXX: is this pr_err or normal/none code path? */
  1006. +       u64_stats_update_begin(&txq->syncp);
  1007. +       txq->tx_dropped++;
  1008. +       u64_stats_update_end(&txq->syncp);
  1009. +
  1010. +       return NETDEV_TX_OK;
  1011. +   }
  1012. +
  1013. +   //TODO is support for more than one queue per cpu per iface overkill?
  1014. +//     ring = &priv->tx[queue_id % MAX_TX_RINGS];
  1015. +   ring = txq->ring;
  1016.  
  1017.  #ifdef SW_ROUTING
  1018.     if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) {
  1019. -       u16 port_map = priv->port_map;
  1020. +       u16 port_map = priv->d_port_map;
  1021.  
  1022. -       if (priv->sw && skb->protocol == htons(ETH_P_8021Q)) {
  1023. +       if ((iface->iftype & BIT(IF_TYPE_SWITCH)) &&
  1024. +           skb->protocol == htons(ETH_P_8021Q)) {
  1025.             u16 vid;
  1026.             int i;
  1027.  
  1028.             port_map = 0;
  1029.             if (!__vlan_get_tag(skb, &vid)) {
  1030.                 for (i = 0; i < XRX200_MAX_VLAN; i++) {
  1031. -                   if (priv->hw->vlan_vid[i] != vid)
  1032. -                       continue;
  1033. -                   port_map = priv->hw->vlan_port_map[i];
  1034. -                   break;
  1035. +                   if (priv->vlan_vid[i] == vid) {
  1036. +                       port_map = priv->vlan_port_map[i];
  1037. +                       break;
  1038. +                   }
  1039.                 }
  1040.             }
  1041.         }
  1042. @@ -1089,109 +1515,327 @@
  1043.         special_tag |= (port_map << PORT_MAP_SHIFT) |
  1044.                    PORT_MAP_SEL | PORT_MAP_EN;
  1045.     }
  1046. -   if(priv->wan)
  1047. +
  1048. +   if (iface->iftype & BIT(IF_TYPE_WAN))
  1049.         special_tag |= (1 << DPID_SHIFT);
  1050. -   if(skb_headroom(skb) < 4) {
  1051. -       struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
  1052. +
  1053. +   if (skb_headroom(skb) < XRX200_HEADROOM) {
  1054. +       struct sk_buff *tmp = skb_realloc_headroom(skb, XRX200_HEADROOM);
  1055.         dev_kfree_skb_any(skb);
  1056.         skb = tmp;
  1057.     }
  1058. -   skb_push(skb, 4);
  1059. +
  1060. +   skb_push(skb, XRX200_HEADROOM);
  1061.     memcpy(skb->data, &special_tag, sizeof(u32));
  1062. -   len += 4;
  1063.  #endif
  1064.  
  1065. -   /* dma needs to start on a 16 byte aligned address */
  1066. -   byte_offset = CPHYSADDR(skb->data) % 16;
  1067. +   if (skb_shinfo(skb)->nr_frags == 0) {
  1068. +       len = skb->len;
  1069. +   } else {
  1070. +       len = skb_headlen(skb);
  1071. +   }
  1072. +
  1073. +   head = txq->head;
  1074.  
  1075. -   spin_lock_bh(&ch->lock);
  1076. -   if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
  1077. -       netdev_err(dev, "tx ring full\n");
  1078. -       netif_stop_queue(dev);
  1079. -       ret = NETDEV_TX_BUSY;
  1080. +   /* Map to DMA first, we cannot fail after ring allocation */
  1081. +
  1082. +   /* map basic fragment of packet */
  1083. +   // TODO,weird : etop uses virt_to_phys, but here it would not work
  1084. +   txq->skb_list[head].addr = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
  1085. +   if (unlikely(dma_mapping_error(priv->dev, txq->skb_list[head].addr))) {
  1086. +       netdev_err(dev, "DMA mapping failed for skb\n");
  1087. +
  1088. +       dev_kfree_skb(skb);
  1089. +
  1090. +       u64_stats_update_begin(&txq->syncp);
  1091. +       txq->tx_dropped++;
  1092. +       txq->tx_errors++;
  1093. +       u64_stats_update_end(&txq->syncp);
  1094. +
  1095. +       ret = NETDEV_TX_OK;
  1096.         goto out;
  1097.     }
  1098.  
  1099. -   ch->skb[ch->dma.desc] = skb;
  1100. +   txq->skb_list[head].size = len;
  1101. +
  1102. +   /* map rest of fragments */
  1103. +   for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  1104. +       const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1105. +
  1106. +       idx = (head + i + 1) % txq->num;
  1107. +
  1108. +       len = skb_frag_size(frag);
  1109. +
  1110. +       txq->skb_list[idx].addr = dma_map_single(priv->dev,
  1111. +                         skb_frag_address(frag),
  1112. +                         len, DMA_TO_DEVICE);
  1113. +
  1114. +       if (unlikely(dma_mapping_error(priv->dev, txq->skb_list[idx].addr))) {
  1115. +           netdev_err(dev, "DMA mapping for fragment #%i failed\n", i);
  1116. +
  1117. +           i--;
  1118. +
  1119. +           for (; i >= 0; i--) {
  1120. +               idx = (head + i + 1) % txq->num;
  1121. +               dma_unmap_single(priv->dev, txq->skb_list[idx].addr,
  1122. +                        txq->skb_list[idx].size,
  1123. +                        DMA_TO_DEVICE);
  1124. +           }
  1125. +
  1126. +           dma_unmap_single(priv->dev, txq->skb_list[head].addr,
  1127. +                    txq->skb_list[head].size, DMA_TO_DEVICE);
  1128. +
  1129. +           dev_kfree_skb(skb);
  1130. +
  1131. +           u64_stats_update_begin(&txq->syncp);
  1132. +           txq->tx_dropped++;
  1133. +           txq->tx_errors++;
  1134. +           u64_stats_update_end(&txq->syncp);
  1135. +
  1136. +           ret = NETDEV_TX_OK;
  1137. +           goto out;
  1138. +       }
  1139. +
  1140. +       txq->skb_list[idx].size = len;
  1141. +   }
  1142. +
  1143. +   /* we need to lock from other queues using the same ring */
  1144. +   spin_lock_irqsave(&ring->lock, flags);
  1145. +
  1146. +   ring_head = ring->dma.desc;
  1147. +
  1148. +   /* check if there is free space in DMA ring */
  1149. +   if (unlikely(TX_BUFFS_AVAIL(ring->free, ring_head, ring->num) <= (MAX_SKB_FRAGS + 1))) {
  1150. +       spin_unlock_irqrestore(&ring->lock, flags);
  1151. +
  1152. +       netif_tx_stop_queue(txq->nqueue);
  1153. +       netdev_err(dev, "not enough space on ring %i\n", queue_id);
  1154. +
  1155. +       for (i = skb_shinfo(skb)->nr_frags; i >= 0; i--) {
  1156. +           idx = (head + i + 1) % txq->num;
  1157. +
  1158. +           dma_unmap_single(priv->dev, txq->skb_list[idx].addr,
  1159. +                    txq->skb_list[idx].size, DMA_TO_DEVICE);
  1160. +       }
  1161. +
  1162. +       dma_unmap_single(priv->dev, txq->skb_list[idx].addr,
  1163. +                txq->skb_list[idx].size, DMA_TO_DEVICE);
  1164. +
  1165. +       return NETDEV_TX_BUSY;
  1166. +   }
  1167. +
  1168. +   /* Allocate the space in DMA ring, we cannot fail, ring shared */
  1169. +   ring->dma.desc = (ring_head + skb_shinfo(skb)->nr_frags + 1) % ring->num;
  1170. +
  1171. +   spin_unlock_irqrestore(&ring->lock, flags);
  1172. +
  1173. +   /* Allocate the space for queue ring */
  1174. +   txq->head = (head + skb_shinfo(skb)->nr_frags + 1) % txq->num;
  1175. +
  1176. +   /* fill all descriptors from queue ring to DMA ring */
  1177. +   for (i = 0; i < skb_shinfo(skb)->nr_frags + 1; i++) {
  1178. +       struct ltq_dma_desc *desc;
  1179. +       struct xrx200_tx_skb *skb_list;
  1180. +       unsigned int ring_idx = (ring_head + i) % ring->num;
  1181. +
  1182. +       desc = &ring->dma.desc_base[ring_idx];
  1183. +       skb_list = &txq->skb_list[(head + i) % txq->num];
  1184.  
  1185. -   netif_trans_update(dev);
  1186. +       skb_list->skb = skb;
  1187. +       skb_list->txq = txq;
  1188.  
  1189. -   desc->addr = ((unsigned int) dma_map_single(ch->dma.dev, skb->data, len,
  1190. -                       DMA_TO_DEVICE)) - byte_offset;
  1191. +       ring->skb_list_ptr[ring_idx] = skb_list;
  1192. +
  1193. +       desc->addr = (skb_list->addr & 0x1fffffe0) | (1<<31);
  1194. +
  1195. +       if (i == 0) {
  1196. +           /* first frag of packet needs SOP, cannot have OWN yet */
  1197. +           desc->ctl = LTQ_DMA_SOP |
  1198. +               LTQ_DMA_TX_OFFSET(skb_list->addr & XRX200_DMA_TX_ALIGN) |
  1199. +               (skb_list->size & LTQ_DMA_SIZE_MASK);
  1200. +       } else {
  1201. +           /* other fragments of a packet can have OWN */
  1202. +           desc->ctl = LTQ_DMA_OWN |
  1203. +               LTQ_DMA_TX_OFFSET(skb_list->addr & XRX200_DMA_TX_ALIGN) |
  1204. +               (skb_list->size & LTQ_DMA_SIZE_MASK);
  1205. +       }
  1206. +
  1207. +       /* the last fragment needs EOP */
  1208. +       if (i == skb_shinfo(skb)->nr_frags)
  1209. +           desc->ctl |= LTQ_DMA_EOP;
  1210. +   }
  1211. +
  1212. +   /* before changing ownership to HW, everything must be written to RAM */
  1213.     wmb();
  1214. -   desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
  1215. -       LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
  1216. -   ch->dma.desc++;
  1217. -   ch->dma.desc %= LTQ_DESC_NUM;
  1218. -   if (ch->dma.desc == ch->tx_free)
  1219. -       netif_stop_queue(dev);
  1220.  
  1221. +   /* Start TX DMA, set OWN for the first fragment */
  1222. +   ring->dma.desc_base[ring_head].ctl |= LTQ_DMA_OWN;
  1223.  
  1224. -   priv->stats.tx_packets++;
  1225. -   priv->stats.tx_bytes+=len;
  1226. +   /* stop the queue until there is enough space in both rings */
  1227. +   if (unlikely((TX_BUFFS_AVAIL(ring->free, ring->dma.desc, ring->num) <= (MAX_SKB_FRAGS + 1)) ||
  1228. +       (TX_BUFFS_AVAIL(txq->tail, txq->head, txq->num) <= (MAX_SKB_FRAGS + 1)))) {
  1229. +       netif_tx_stop_queue(txq->nqueue);
  1230. +   }
  1231.  
  1232. -out:
  1233. -   spin_unlock_bh(&ch->lock);
  1234. +   skb_tx_timestamp(skb);
  1235.  
  1236. +out:
  1237.     return ret;
  1238.  }
  1239.  
  1240. -static irqreturn_t xrx200_dma_irq(int irq, void *priv)
  1241. +//NOTICE irq events must be as low as possible (big overhead on slow CPU)
  1242. +static irqreturn_t xrx200_tx_dma_irq(int irq, void *ptr)
  1243.  {
  1244. -   struct xrx200_hw *hw = priv;
  1245. -   int chnr = irq - XRX200_DMA_IRQ;
  1246. -   struct xrx200_chan *ch = &hw->chan[chnr];
  1247. +   struct xrx200_tx_ring *ring = ptr;
  1248.  
  1249. -   ltq_dma_disable_irq(&ch->dma);
  1250. -   ltq_dma_ack_irq(&ch->dma);
  1251. +   ltq_dma_disable_irq(&ring->dma);
  1252. +   ltq_dma_ack_irq(&ring->dma);
  1253.  
  1254. -   if (chnr % 2)
  1255. -       tasklet_schedule(&ch->tasklet);
  1256. -   else
  1257. -       napi_schedule(&ch->napi);
  1258. +   napi_schedule_irqoff(&ring->napi);
  1259. +   return IRQ_HANDLED;
  1260. +}
  1261. +
  1262. +//NOTICE it would be nice to have IRQ events in rx as low as possible too, how?
  1263. +static irqreturn_t xrx200_rx_dma_irq(int irq, void *ptr)
  1264. +{
  1265. +   struct xrx200_rx_ring *ring = ptr;
  1266. +
  1267. +   ltq_dma_disable_irq(&ring->dma);
  1268. +   ltq_dma_ack_irq(&ring->dma);
  1269. +
  1270. +   napi_schedule_irqoff(&ring->napi);
  1271.  
  1272.     return IRQ_HANDLED;
  1273.  }
  1274.  
  1275. -static int xrx200_dma_init(struct device *dev, struct xrx200_hw *hw)
  1276. +
  1277. +static int xrx200_dma_init(struct xrx200_priv *priv)
  1278.  {
  1279. -   int i, err = 0;
  1280. +   int i;
  1281. +   int ret;
  1282. +   char *irq_name;
  1283.  
  1284.     ltq_dma_init_port(DMA_PORT_ETOP);
  1285.  
  1286. -   for (i = 0; i < 8 && !err; i++) {
  1287. -       int irq = XRX200_DMA_IRQ + i;
  1288. -       struct xrx200_chan *ch = &hw->chan[i];
  1289. -
  1290. -       spin_lock_init(&ch->lock);
  1291. -
  1292. -       ch->idx = ch->dma.nr = i;
  1293. -       ch->dma.dev = dev;
  1294. -
  1295. -       if (i == XRX200_DMA_TX) {
  1296. -           ltq_dma_alloc_tx(&ch->dma);
  1297. -           err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
  1298. -       } else if (i == XRX200_DMA_TX_2) {
  1299. -           ltq_dma_alloc_tx(&ch->dma);
  1300. -           err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx_2", hw);
  1301. -       } else if (i == XRX200_DMA_RX) {
  1302. -           ltq_dma_alloc_rx(&ch->dma);
  1303. -           for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
  1304. -                   ch->dma.desc++)
  1305. -               if (xrx200_alloc_skb(ch))
  1306. -                   err = -ENOMEM;
  1307. -           ch->dma.desc = 0;
  1308. -           err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw);
  1309. -       } else
  1310. -           continue;
  1311. +   //TODO external definitions?
  1312. +   priv->rx[0].dma.irq = XRX200_DMA_IRQ + XRX200_DMA_RX;
  1313. +   priv->rx[0].dma.nr = XRX200_DMA_RX;
  1314. +
  1315. +   //TODO into ltq_dma_channel?
  1316. +   priv->rx[0].num = LTQ_DESC_NUM;
  1317. +
  1318. +   for (i = 0; i < MAX_RX_RINGS; i++) {
  1319. +       struct xrx200_rx_ring *ring = &priv->rx[i];
  1320. +       int idx;
  1321. +
  1322. +       ring->dma.dev = priv->dev;
  1323. +       ring->priv = priv;
  1324. +
  1325. +       ltq_dma_alloc_rx(&ring->dma);   //TODO add ring num
  1326. +
  1327. +       //TODO into ltq_dma_channel?
  1328. +       ring->skb_list = devm_kzalloc(priv->dev, ring->num *
  1329. +                   sizeof(struct xrx200_rx_skb), GFP_KERNEL);
  1330. +
  1331. +       //TODO is null
  1332. +
  1333. +       /* NOTICE this will be incremented in xrx200_alloc_skb */
  1334. +       ring->dma.desc = 0;
  1335. +
  1336. +       for (idx = 0; idx < ring->num; idx++) {
  1337. +           ret = xrx200_alloc_skb(priv, &ring->dma,
  1338. +                          &ring->skb_list[idx]);
  1339. +           if (ret)
  1340. +               #warning "TODO ERROR PATHS"
  1341. +               goto rx_free;
  1342. +       }
  1343. +
  1344. +       /* NOTICE reset "head" after xrx200_alloc_skb */
  1345. +       ring->dma.desc = 0;
  1346. +
  1347. +       irq_name = devm_kasprintf(priv->dev, GFP_KERNEL, "xrx200-net rx%d", i);
  1348. +       //TODO null
  1349. +
  1350. +       ret = devm_request_irq(priv->dev, ring->dma.irq, xrx200_rx_dma_irq, 0,
  1351. +                      irq_name, ring);
  1352. +       if (ret) {
  1353. +           dev_err(priv->dev, "failed to request RX irq %d\n",
  1354. +               ring->dma.irq);
  1355. +           goto rx_ring_free;
  1356. +       }
  1357.  
  1358. -       if (!err)
  1359. -           ch->dma.irq = irq;
  1360. -       else
  1361. -           pr_err("net-xrx200: failed to request irq %d\n", irq);
  1362.     }
  1363.  
  1364. -   return err;
  1365. +   //TODO TX rings vs cpuid nr_cpu_ids
  1366. +
  1367. +   //TODO this is HACK, devicetree? or at least array
  1368. +   priv->tx[0].dma.irq = XRX200_DMA_IRQ + XRX200_DMA_TX;
  1369. +   priv->tx[0].dma.nr = XRX200_DMA_TX;
  1370. +   priv->tx[0].num = LTQ_DESC_NUM;
  1371. +   priv->tx[1].dma.irq = XRX200_DMA_IRQ + XRX200_DMA_TX_2;
  1372. +   priv->tx[1].dma.nr = XRX200_DMA_TX_2;
  1373. +   priv->tx[1].num = LTQ_DESC_NUM;
  1374. +
  1375. +
  1376. +   for (i = 0; i < MAX_TX_RINGS; i++) {
  1377. +       struct xrx200_tx_ring *ring = &priv->tx[i];
  1378. +       ring->dma.dev = priv->dev;
  1379. +
  1380. +       ring->priv = priv;
  1381. +
  1382. +       spin_lock_init(&ring->lock);
  1383. +
  1384. +
  1385. +       ltq_dma_alloc_tx(&ring->dma);
  1386. +
  1387. +       ring->free = 0;
  1388. +
  1389. +
  1390. +       INIT_LIST_HEAD(&ring->queues);
  1391. +
  1392. +       /* array of pointers */
  1393. +       ring->skb_list_ptr = devm_kzalloc(priv->dev, ring->num *
  1394. +           sizeof(struct xrx200_tx_skb *), GFP_KERNEL);
  1395. +       //TODO err path
  1396. +
  1397. +       irq_name = devm_kasprintf(priv->dev, GFP_KERNEL, "xrx200-net tx%d", i);
  1398. +
  1399. +       //TODO err path
  1400. +
  1401. +       ret = devm_request_irq(priv->dev, ring->dma.irq, xrx200_tx_dma_irq, 0,
  1402. +                      irq_name, ring);
  1403. +
  1404. +       if (ret) {
  1405. +           dev_err(priv->dev, "failed to request TX irq %d\n",
  1406. +               ring->dma.irq);
  1407. +
  1408. +           for (; i >= 0; i--) {
  1409. +               ltq_dma_free(&ring->dma);
  1410. +           }
  1411. +
  1412. +           goto rx_ring_free;
  1413. +       }
  1414. +   }
  1415. +
  1416. +   return ret;
  1417. +
  1418. +rx_ring_free:
  1419. +
  1420. +
  1421. +rx_free:
  1422. +return ret;
  1423. +//TODO redo
  1424. +#if 0
  1425. +   /* free the allocated RX ring */
  1426. +   for (i = 0; i < LTQ_DESC_NUM; i++) {
  1427. +       if (rxq->dma_skb[i].skb)
  1428. +           dev_kfree_skb_any(rxq->dma_skb[i].skb);
  1429. +   }
  1430. +
  1431. +rx_free:
  1432. +   ltq_dma_free(&rxq->dma);
  1433. +   return ret;
  1434. +#endif
  1435.  }
  1436.  
  1437.  #ifdef SW_POLLING
  1438. @@ -1249,19 +1893,22 @@
  1439.  
  1440.  static void xrx200_mdio_link(struct net_device *dev)
  1441.  {
  1442. -   struct xrx200_priv *priv = netdev_priv(dev);
  1443. -   int i;
  1444. +   struct xrx200_iface *iface = netdev_priv(dev);
  1445. +   struct list_head *pos;
  1446. +
  1447. +   list_for_each(pos, &iface->ports) {
  1448. +       struct xrx200_port *port = list_entry(pos, struct xrx200_port,
  1449. +                             port);
  1450.  
  1451. -   for (i = 0; i < priv->num_port; i++) {
  1452. -       if (!priv->port[i].phydev)
  1453. +       if (!port->phydev)
  1454.             continue;
  1455.  
  1456. -       if (priv->port[i].link != priv->port[i].phydev->link) {
  1457. -           xrx200_gmac_update(&priv->port[i]);
  1458. -           priv->port[i].link = priv->port[i].phydev->link;
  1459. +       if (port->link != port->phydev->link) {
  1460. +           xrx200_gmac_update(port);
  1461. +           port->link = port->phydev->link;
  1462.             netdev_info(dev, "port %d %s link\n",
  1463. -               priv->port[i].num,
  1464. -               (priv->port[i].link)?("got"):("lost"));
  1465. +                   port->num,
  1466. +                   (port->link)?("got"):("lost"));
  1467.         }
  1468.     }
  1469.  }
  1470. @@ -1311,14 +1958,16 @@
  1471.  
  1472.  static int xrx200_phy_has_link(struct net_device *dev)
  1473.  {
  1474. -   struct xrx200_priv *priv = netdev_priv(dev);
  1475. -   int i;
  1476. +   struct xrx200_iface *iface = netdev_priv(dev);
  1477. +   struct list_head *pos;
  1478.  
  1479. -   for (i = 0; i < priv->num_port; i++) {
  1480. -       if (!priv->port[i].phydev)
  1481. +   list_for_each(pos, &iface->ports) {
  1482. +       struct xrx200_port *port = list_entry(pos, struct xrx200_port,
  1483. +                             port);
  1484. +       if (!port->phydev)
  1485.             continue;
  1486.  
  1487. -       if (priv->port[i].phydev->link)
  1488. +       if (port->phydev->link)
  1489.             return 1;
  1490.     }
  1491.  
  1492. @@ -1341,11 +1990,14 @@
  1493.  
  1494.  static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
  1495.  {
  1496. -   struct xrx200_priv *priv = netdev_priv(dev);
  1497. +   struct xrx200_iface *iface = netdev_priv(dev);
  1498. +   struct xrx200_priv *priv = iface->priv;
  1499.     struct phy_device *phydev = NULL;
  1500. +#ifdef SW_POLLING
  1501.     unsigned val;
  1502. +#endif
  1503.  
  1504. -   phydev = mdiobus_get_phy(priv->hw->mii_bus, port->phy_addr);
  1505. +   phydev = mdiobus_get_phy(priv->mii_bus, port->phy_addr);
  1506.  
  1507.     if (!phydev) {
  1508.         netdev_err(dev, "no PHY found\n");
  1509. @@ -1378,10 +2030,10 @@
  1510.  #ifdef SW_POLLING
  1511.     phy_read_status(phydev);
  1512.  
  1513. -   val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
  1514. +   val = xrx200_mdio_rd(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
  1515.     val |= ADVERTIZE_MPD;
  1516. -   xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
  1517. -   xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040);
  1518. +   xrx200_mdio_wr(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
  1519. +   xrx200_mdio_wr(priv->mii_bus, 0, 0, 0x1040);
  1520.  
  1521.     phy_start_aneg(phydev);
  1522.  #endif
  1523. @@ -1458,27 +2110,23 @@
  1524.  
  1525.  static int xrx200_init(struct net_device *dev)
  1526.  {
  1527. -   struct xrx200_priv *priv = netdev_priv(dev);
  1528. +   struct xrx200_iface *iface = netdev_priv(dev);
  1529. +   struct xrx200_priv *priv = iface->priv;
  1530. +   struct xrx200_port *port;
  1531.     struct sockaddr mac;
  1532. -   int err, i;
  1533. -
  1534. -#ifndef SW_POLLING
  1535. -   unsigned int reg = 0;
  1536. -
  1537. -   /* enable auto polling */
  1538. -   for (i = 0; i < priv->num_port; i++)
  1539. -       reg |= BIT(priv->port[i].num);
  1540. -   ltq_mdio_w32(reg, MDIO_CLK_CFG0);
  1541. -   ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
  1542. -#endif
  1543. +   int err;
  1544. +   struct list_head *pos;
  1545.  
  1546.     /* setup each port */
  1547. -   for (i = 0; i < priv->num_port; i++)
  1548. -       xrx200_port_config(priv, &priv->port[i]);
  1549. +   list_for_each(pos, &iface->ports) {
  1550. +       port = list_entry(pos, struct xrx200_port, port);
  1551. +
  1552. +       xrx200_port_config(priv, port);
  1553. +   }
  1554.  
  1555. -   memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
  1556. +   memcpy(&mac.sa_data, iface->mac, ETH_ALEN);
  1557.     if (!is_valid_ether_addr(mac.sa_data)) {
  1558. -       pr_warn("net-xrx200: invalid MAC, using random\n");
  1559. +       netdev_warn(dev, "net-xrx200: invalid MAC, using random\n");
  1560.         eth_random_addr(mac.sa_data);
  1561.         dev->addr_assign_type |= NET_ADDR_RANDOM;
  1562.     }
  1563. @@ -1487,16 +2135,20 @@
  1564.     if (err)
  1565.         goto err_netdev;
  1566.  
  1567. -   for (i = 0; i < priv->num_port; i++)
  1568. -       if (xrx200_mdio_probe(dev, &priv->port[i]))
  1569. -           pr_warn("xrx200-mdio: probing phy of port %d failed\n",
  1570. -                    priv->port[i].num);
  1571. +   list_for_each(pos, &iface->ports) {
  1572. +       port = list_entry(pos, struct xrx200_port, port);
  1573. +
  1574. +       if (xrx200_mdio_probe(dev, port))
  1575. +           netdev_warn(dev, "xrx200-mdio: probing phy of port %d failed\n",
  1576. +                    port->num);
  1577. +           //TODO error path
  1578. +   }
  1579.  
  1580.     return 0;
  1581.  
  1582.  err_netdev:
  1583.     unregister_netdev(dev);
  1584. -   free_netdev(dev);
  1585. +   //free_netdev(dev); //devm?? TODO
  1586.     return err;
  1587.  }
  1588.  
  1589. @@ -1524,19 +2176,20 @@
  1590.     ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0));
  1591.  }
  1592.  
  1593. -static void xrx200_hw_init(struct xrx200_hw *hw)
  1594. +static void xrx200_hw_init(struct xrx200_priv *priv)
  1595.  {
  1596.     int i;
  1597.  
  1598.     /* enable clock gate */
  1599. -   clk_enable(hw->clk);
  1600. +   clk_enable(priv->clk);
  1601.  
  1602.     ltq_switch_w32(1, 0);
  1603.     mdelay(100);
  1604.     ltq_switch_w32(0, 0);
  1605. +
  1606.     /*
  1607. -    * TODO: we should really disbale all phys/miis here and explicitly
  1608. -    * enable them in the device secific init function
  1609. +    * TODO: we should really disable all phys/miis here and explicitly
  1610. +    * enable them in the device specific init function
  1611.      */
  1612.  
  1613.     /* disable port fetch/store dma */
  1614. @@ -1556,16 +2209,18 @@
  1615.     ltq_switch_w32(0x40, PCE_PMAP2);
  1616.     ltq_switch_w32(0x40, PCE_PMAP3);
  1617.  
  1618. +//TODO search XRX200_BM_GCTRL_FR_RBC
  1619. +
  1620.     /* RMON Counter Enable for all physical ports */
  1621. -   for (i = 0; i < 7; i++)
  1622. -       ltq_switch_w32(0x1, BM_PCFG(i));
  1623. +// for (i = 0; i < 7; i++)
  1624. +//     ltq_switch_w32(0x1, BM_PCFG(i));
  1625.  
  1626.     /* disable auto polling */
  1627.     ltq_mdio_w32(0x0, MDIO_CLK_CFG0);
  1628.  
  1629.     /* enable port statistic counters */
  1630. -   for (i = 0; i < 7; i++)
  1631. -       ltq_switch_w32(0x1, BM_PCFGx(i));
  1632. +// for (i = 0; i < 7; i++)
  1633. +//     ltq_switch_w32(0x1, BM_PCFGx(i));
  1634.  
  1635.     /* set IPG to 12 */
  1636.     ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG);
  1637. @@ -1597,68 +2252,92 @@
  1638.     xrx200sw_write_x(1, XRX200_BM_QUEUE_GCTRL_GL_MOD, 0);
  1639.  
  1640.     for (i = 0; i < XRX200_MAX_VLAN; i++)
  1641. -       hw->vlan_vid[i] = i;
  1642. +       priv->vlan_vid[i] = i;
  1643.  }
  1644.  
  1645. -static void xrx200_hw_cleanup(struct xrx200_hw *hw)
  1646. +static void xrx200_hw_cleanup(struct xrx200_priv *priv)
  1647.  {
  1648. -   int i;
  1649. +   int i, idx;
  1650.  
  1651.     /* disable the switch */
  1652.     ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB);
  1653.  
  1654. -   /* free the channels and IRQs */
  1655. -   for (i = 0; i < 2; i++) {
  1656. -       ltq_dma_free(&hw->chan[i].dma);
  1657. -       if (hw->chan[i].dma.irq)
  1658. -           free_irq(hw->chan[i].dma.irq, hw);
  1659. +
  1660. +   for (i = 0; i < MAX_TX_RINGS; i++) {
  1661. +       struct xrx200_tx_ring *ring = &priv->tx[i];
  1662. +
  1663. +       ltq_dma_free(&ring->dma);
  1664. +
  1665. +//TODO cleanup path
  1666. +//     ring->dma.desc_base = NULL;
  1667.     }
  1668.  
  1669. -   /* free the allocated RX ring */
  1670. -   for (i = 0; i < LTQ_DESC_NUM; i++)
  1671. -       dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]);
  1672. +   for (i = 0; i < MAX_RX_RINGS; i++) {
  1673. +       struct xrx200_rx_ring *ring = &priv->rx[i];
  1674. +
  1675. +       ltq_dma_free(&ring->dma);
  1676. +
  1677. +       /* free the allocated RX ring */
  1678. +       for (idx = 0; idx < ring->num; idx++) {
  1679. +           if (ring->skb_list[idx].skb)
  1680. +               dev_kfree_skb_any(ring->skb_list[idx].skb);
  1681. +
  1682. +           ring->skb_list[idx].skb = NULL;
  1683. +       }
  1684. +   }
  1685.  
  1686.     /* clear the mdio bus */
  1687. -   mdiobus_unregister(hw->mii_bus);
  1688. -   mdiobus_free(hw->mii_bus);
  1689. +   mdiobus_unregister(priv->mii_bus);
  1690. +   mdiobus_free(priv->mii_bus);
  1691.  
  1692.     /* release the clock */
  1693. -   clk_disable(hw->clk);
  1694. -   clk_put(hw->clk);
  1695. +   clk_disable(priv->clk);
  1696. +   clk_put(priv->clk);
  1697.  }
  1698.  
  1699. -static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np)
  1700. +static int xrx200_of_mdio(struct xrx200_priv *priv, struct device_node *np)
  1701.  {
  1702. -   hw->mii_bus = mdiobus_alloc();
  1703. -   if (!hw->mii_bus)
  1704. +   priv->mii_bus = mdiobus_alloc();
  1705. +   if (!priv->mii_bus)
  1706.         return -ENOMEM;
  1707.  
  1708. -   hw->mii_bus->read = xrx200_mdio_rd;
  1709. -   hw->mii_bus->write = xrx200_mdio_wr;
  1710. -   hw->mii_bus->name = "lantiq,xrx200-mdio";
  1711. -   snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
  1712. +   priv->mii_bus->read = xrx200_mdio_rd;
  1713. +   priv->mii_bus->write = xrx200_mdio_wr;
  1714. +   priv->mii_bus->name = "lantiq,xrx200-mdio";
  1715. +   snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
  1716.  
  1717. -   if (of_mdiobus_register(hw->mii_bus, np)) {
  1718. -       mdiobus_free(hw->mii_bus);
  1719. +   if (of_mdiobus_register(priv->mii_bus, np)) {
  1720. +       mdiobus_free(priv->mii_bus);
  1721.         return -ENXIO;
  1722.     }
  1723.  
  1724.     return 0;
  1725.  }
  1726.  
  1727. -static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port)
  1728. +static int xrx200_of_port(struct xrx200_priv *priv, struct xrx200_iface *iface, struct device_node *port)
  1729.  {
  1730.     const __be32 *addr, *id = of_get_property(port, "reg", NULL);
  1731. -   struct xrx200_port *p = &priv->port[priv->num_port];
  1732. +   struct xrx200_port *p;
  1733.  
  1734.     if (!id)
  1735. -       return;
  1736. +       return -EINVAL;
  1737. +
  1738. +   p = devm_kzalloc(priv->dev, sizeof(struct xrx200_port),
  1739. +                GFP_KERNEL);
  1740. +   if (!p) {
  1741. +       dev_err(priv->dev, "failed to allocate port structure\n");
  1742. +
  1743. +       return -ENOMEM;
  1744. +   }
  1745.  
  1746. -   memset(p, 0, sizeof(struct xrx200_port));
  1747.     p->phy_node = of_parse_phandle(port, "phy-handle", 0);
  1748.     addr = of_get_property(p->phy_node, "reg", NULL);
  1749. -   if (!addr)
  1750. -       return;
  1751. +
  1752. +   if (!addr) {
  1753. +       dev_err(priv->dev, "property 'reg' is missing\n");
  1754. +
  1755. +       return -EINVAL;
  1756. +   }
  1757.  
  1758.     p->num = *id;
  1759.     p->phy_addr = *addr;
  1760. @@ -1667,7 +2346,6 @@
  1761.         p->flags = XRX200_PORT_TYPE_MAC;
  1762.     else
  1763.         p->flags = XRX200_PORT_TYPE_PHY;
  1764. -   priv->num_port++;
  1765.  
  1766.     p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags);
  1767.     if (gpio_is_valid(p->gpio))
  1768. @@ -1677,16 +2355,108 @@
  1769.             udelay(100);
  1770.             gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
  1771.         }
  1772. +
  1773.     /* is this port a wan port ? */
  1774. -   if (priv->wan)
  1775. -       priv->hw->wan_map |= BIT(p->num);
  1776. +   if (iface->iftype & BIT(IF_TYPE_WAN))
  1777. +       priv->wan_map |= BIT(p->num);
  1778.  
  1779. -   priv->port_map |= BIT(p->num);
  1780. +   priv->d_port_map |= BIT(p->num);
  1781.  
  1782.     /* store the port id in the hw struct so we can map ports -> devices */
  1783. -   priv->hw->port_map[p->num] = priv->hw->num_devs;
  1784. +   priv->port_map[p->num] = iface;
  1785. +
  1786. +   list_add(&p->port, &iface->ports);
  1787. +
  1788. +   return 0;
  1789.  }
  1790.  
  1791. +static void xrx200_get_stats64(struct net_device *dev,
  1792. +                  struct rtnl_link_stats64 *storage)
  1793. +{
  1794. +   struct xrx200_iface *iface = netdev_priv(dev);
  1795. +   unsigned int start;
  1796. +   int i;
  1797. +
  1798. +   //TODO are there HW registers?
  1799. +
  1800. +   do {
  1801. +       start = u64_stats_fetch_begin_irq(&iface->syncp);
  1802. +       storage->tx_errors = iface->tx_errors;
  1803. +   } while (u64_stats_fetch_retry_irq(&iface->syncp, start));
  1804. +
  1805. +   for (i = 0; i < iface->num_tx_queues; i++) {
  1806. +       do {
  1807. +           start = u64_stats_fetch_begin_irq(&iface->txq[i].syncp);
  1808. +           storage->tx_packets += iface->txq[i].tx_packets;
  1809. +           storage->tx_bytes += iface->txq[i].tx_bytes;
  1810. +           storage->tx_errors += iface->txq[i].tx_errors;
  1811. +           storage->tx_dropped += iface->txq[i].tx_dropped;
  1812. +       } while (u64_stats_fetch_retry_irq(&iface->txq[i].syncp, start));
  1813. +   }
  1814. +
  1815. +   do {
  1816. +       start = u64_stats_fetch_begin_irq(&iface->rxq[0].syncp);
  1817. +       storage->rx_packets = iface->rxq[0].rx_packets;
  1818. +       storage->rx_bytes = iface->rxq[0].rx_bytes;
  1819. +       storage->rx_dropped = iface->rxq[0].rx_dropped;
  1820. +   } while (u64_stats_fetch_retry_irq(&iface->rxq[0].syncp, start));
  1821. +
  1822. +}
  1823. +
  1824. +//TODO this too?
  1825. +// * int (*ndo_change_mtu)(struct net_device *dev, int new_mtu);
  1826. +// *   Called when a user wants to change the Maximum Transfer Unit
  1827. +// *   of a device.
  1828. +
  1829. +u16 glqid=0;
  1830. +
  1831. +static u16 xrx200_select_queue(struct net_device *dev, struct sk_buff *skb,
  1832. +               void *accel_priv, select_queue_fallback_t fallback)
  1833. +{
  1834. +   u16 qid;
  1835. +
  1836. +   /*
  1837. +    * TODO?
  1838. +    * The SoC seems to be slowed down by tx housekeeping
  1839. +    * for the highest speed you need to schedule tx housekeeping
  1840. +    * interrupt to the other VPE
  1841. +    *
  1842. +    * The default netdev queue select causes TX speed drops as
  1843. +    * userspace is sometimes scheduled to the same VPE which is making
  1844. +    * housekeeping.
  1845. +    *
  1846. +    * The TX DMAs IRQ should be constrained to a single VPE as the
  1847. +    * cycling through them will cause 50% of time to have the housekeeping
  1848. +    * on the same VPE.
  1849. +    */
  1850. +
  1851. +   //TODO cornercases: single queue, singlecore, constrained affinity
  1852. +
  1853. +
  1854. +#if 0
  1855. +   if (skb_rx_queue_recorded(skb))
  1856. +       qid = skb_get_rx_queue(skb);
  1857. +   else
  1858. +       qid = fallback(dev, skb);
  1859. +//#else
  1860. +//     qid = glqid?1:0;
  1861. +
  1862. +//     glqid = !glqid;
  1863. +#endif
  1864. +
  1865. +   //https://elixir.bootlin.com/linux/v5.1-rc5/source/kernel/irq/cpuhotplug.c#L39
  1866. +
  1867. +   //HACK only two VPEs max
  1868. +   if (smp_processor_id()) {
  1869. +       qid = 0;
  1870. +   } else {
  1871. +       qid = 1;
  1872. +   }
  1873. +
  1874. +   return qid;
  1875. +}
  1876. +
  1877. +
  1878.  static const struct net_device_ops xrx200_netdev_ops = {
  1879.     .ndo_init       = xrx200_init,
  1880.     .ndo_open       = xrx200_open,
  1881. @@ -1694,174 +2464,321 @@
  1882.     .ndo_start_xmit     = xrx200_start_xmit,
  1883.     .ndo_set_mac_address    = eth_mac_addr,
  1884.     .ndo_validate_addr  = eth_validate_addr,
  1885. -   .ndo_get_stats      = xrx200_get_stats,
  1886.     .ndo_tx_timeout     = xrx200_tx_timeout,
  1887. +   .ndo_get_stats64    = xrx200_get_stats64,
  1888. +//     .ndo_select_queue   = xrx200_select_queue,
  1889.  };
  1890.  
  1891. -static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface, struct device *dev)
  1892. +static int xrx200_of_iface(struct xrx200_priv *priv, struct device_node *node, struct device *dev)
  1893.  {
  1894. -   struct xrx200_priv *priv;
  1895.     struct device_node *port;
  1896. -   const __be32 *wan;
  1897. +//     const __be32 *wan;
  1898.     const u8 *mac;
  1899. +   struct net_device *net_dev;
  1900. +   struct xrx200_iface *iface;
  1901. +   int ret;
  1902. +   int i;
  1903.  
  1904. +   /* get interface MII value */
  1905. +//     const __be32 *id = of_get_property(port, "reg", NULL);
  1906. +
  1907. +   //TODO add queues + ring mapping user definition into devicetree
  1908. +
  1909. +   //TODO hardcoded num queues
  1910. +   //NOTICE allocated iface struct
  1911.     /* alloc the network device */
  1912. -   hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
  1913. -   if (!hw->devs[hw->num_devs])
  1914. -       return;
  1915. +   net_dev = devm_alloc_etherdev_mqs(dev, sizeof(struct xrx200_iface),
  1916. +                     MAX_TX_QUEUES, 1);
  1917. +
  1918. +   if (!net_dev) {
  1919. +       dev_err(priv->dev, "failed to allocate net device\n");
  1920. +
  1921. +       return -ENOMEM;
  1922. +   }
  1923. +
  1924. +   //NOTICE iface struct allocated in etherdev mqs
  1925. +   iface = netdev_priv(net_dev);
  1926. +
  1927. +   //TODO iface is array after netdev, container_of?
  1928. +   iface->net_dev = net_dev;
  1929. +   iface->priv = priv;
  1930. +   iface->num_tx_queues = 2;   //TODO devicetree?
  1931. +
  1932. +   net_dev->netdev_ops = &xrx200_netdev_ops;   //TODO dvakrat
  1933. +   SET_NETDEV_DEV(net_dev, priv->dev);
  1934. +   net_dev->min_mtu = ETH_ZLEN;
  1935. +   net_dev->max_mtu = XRX200_DMA_DATA_LEN;
  1936. +
  1937. +   net_dev->features |= NETIF_F_SG ;
  1938. +   net_dev->hw_features |= NETIF_F_SG;
  1939. +   net_dev->vlan_features |= NETIF_F_SG;
  1940.  
  1941.     /* setup the network device */
  1942. -   strcpy(hw->devs[hw->num_devs]->name, "eth%d");
  1943. -   hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops;
  1944. -   hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT;
  1945. -   hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM;
  1946. -   SET_NETDEV_DEV(hw->devs[hw->num_devs], dev);
  1947. -
  1948. -   /* setup our private data */
  1949. -   priv = netdev_priv(hw->devs[hw->num_devs]);
  1950. -   priv->hw = hw;
  1951. -   priv->id = hw->num_devs;
  1952. +   strcpy(net_dev->name, "eth%d");
  1953. +   net_dev->netdev_ops = &xrx200_netdev_ops;
  1954. +   net_dev->watchdog_timeo = XRX200_TX_TIMEOUT;
  1955. +   net_dev->needed_headroom = XRX200_HEADROOM;
  1956.  
  1957. -   mac = of_get_mac_address(iface);
  1958. +   mac = of_get_mac_address(node);
  1959.     if (mac)
  1960. -       memcpy(priv->mac, mac, ETH_ALEN);
  1961. +       memcpy(iface->mac, mac, ETH_ALEN);
  1962. +
  1963. +   /* should the switch be enabled on this interface ? */
  1964. +   if (of_find_property(node, "lantiq,switch", NULL))
  1965. +       iface->iftype |= BIT(IF_TYPE_SWITCH);
  1966.  
  1967.     /* is this the wan interface ? */
  1968. -   wan = of_get_property(iface, "lantiq,wan", NULL);
  1969. -   if (wan && (*wan == 1))
  1970. -       priv->wan = 1;
  1971. +   if (of_find_property(node, "lantiq,wan", NULL))
  1972. +       iface->iftype |= BIT(IF_TYPE_WAN);
  1973.  
  1974. -   /* should the switch be enabled on this interface ? */
  1975. -   if (of_find_property(iface, "lantiq,switch", NULL))
  1976. -       priv->sw = 1;
  1977. +   INIT_LIST_HEAD(&iface->ports);
  1978.  
  1979.     /* load the ports that are part of the interface */
  1980. -   for_each_child_of_node(iface, port)
  1981. +   for_each_child_of_node(node, port)
  1982.         if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
  1983. -           xrx200_of_port(priv, port);
  1984. +           if (xrx200_of_port(priv, iface, port)) {
  1985. +               return -EINVAL;
  1986. +           }
  1987.  
  1988. -   /* register the actual device */
  1989. -   if (!register_netdev(hw->devs[hw->num_devs]))
  1990. -       hw->num_devs++;
  1991. -}
  1992. +   iface->txq = devm_kzalloc(priv->dev, iface->num_tx_queues *
  1993. +                 sizeof(struct xrx200_tx_queue),
  1994. +                 GFP_KERNEL);
  1995. +
  1996. +   iface->rxq = devm_kzalloc(priv->dev, sizeof(struct xrx200_rx_queue),
  1997. +                 GFP_KERNEL);
  1998. +
  1999. +   for (i = 0; i < iface->num_tx_queues; i++) {
  2000. +       struct xrx200_tx_queue *txq = &iface->txq[i];
  2001. +       //TODO shorten by txq pointer
  2002. +
  2003. +       txq->ring = &priv->tx[i % MAX_TX_RINGS];
  2004. +       txq->nqueue = netdev_get_tx_queue(net_dev, i % MAX_TX_RINGS);
  2005. +
  2006. +       /* local ring pointers */
  2007. +       txq->head = 0;
  2008. +       txq->tail = 0;
  2009.  
  2010. -static struct xrx200_hw xrx200_hw;
  2011. +       //split from ring length
  2012. +       txq->num = txq->ring->num / 1;
  2013. +       //TODO divide by queue count per ring list_for_each txq->ring->queues
  2014. +
  2015. +       /* array of descriptors */
  2016. +       txq->skb_list = devm_kzalloc(priv->dev,
  2017. +                        txq->num * sizeof(struct xrx200_tx_skb),
  2018. +                        GFP_KERNEL);
  2019. +
  2020. +       //queue can be more than cpus
  2021. +
  2022. +       list_add(&txq->queue, &txq->ring->queues);
  2023. +   }
  2024. +
  2025. +   iface->rxq[0].priv = priv;
  2026. +   iface->rxq[0].ring = &priv->rx[0];
  2027. +
  2028. +   ret = register_netdev(net_dev);
  2029. +   if (ret)
  2030. +       return ret;
  2031. +
  2032. +   if (iface->iftype & BIT(IF_TYPE_SWITCH))
  2033. +       xrx200sw_init(iface);
  2034. +
  2035. +   list_add(&iface->iface, &priv->ifaces);
  2036. +
  2037. +   return 0;
  2038. +}
  2039.  
  2040.  static int xrx200_probe(struct platform_device *pdev)
  2041.  {
  2042. +   struct device *dev = &pdev->dev;
  2043.     struct resource *res[4];
  2044.     struct device_node *mdio_np, *iface_np, *phy_np;
  2045.     struct of_phandle_iterator it;
  2046.     int err;
  2047.     int i;
  2048. +   struct xrx200_priv *priv;
  2049. +#ifndef SW_POLLING
  2050. +   struct list_head *pos;
  2051. +   unsigned int reg = 0;
  2052. +#endif
  2053. +
  2054. +   priv = devm_kzalloc(dev, sizeof(struct xrx200_priv),
  2055. +            GFP_KERNEL);
  2056. +   if (!priv) {
  2057. +       dev_err(dev, "failed to allocate priv structure\n");
  2058. +
  2059. +       return -ENOMEM;
  2060. +   }
  2061. +
  2062. +   priv->dev = dev;
  2063. +
  2064. +//dev_set_drvdata(dev, priv); ???
  2065.  
  2066.     /* load the memory ranges */
  2067.     for (i = 0; i < 4; i++) {
  2068.         res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
  2069.         if (!res[i]) {
  2070. -           dev_err(&pdev->dev, "failed to get resources\n");
  2071. +           dev_err(dev, "failed to get resources\n");
  2072.             return -ENOENT;
  2073.         }
  2074.     }
  2075. -   xrx200_switch_membase = devm_ioremap_resource(&pdev->dev, res[0]);
  2076. -   xrx200_mdio_membase = devm_ioremap_resource(&pdev->dev, res[1]);
  2077. -   xrx200_mii_membase = devm_ioremap_resource(&pdev->dev, res[2]);
  2078. -   xrx200_pmac_membase = devm_ioremap_resource(&pdev->dev, res[3]);
  2079. +
  2080. +   xrx200_switch_membase = devm_ioremap_resource(dev, res[0]);
  2081. +   xrx200_mdio_membase = devm_ioremap_resource(dev, res[1]);
  2082. +   xrx200_mii_membase = devm_ioremap_resource(dev, res[2]);
  2083. +   xrx200_pmac_membase = devm_ioremap_resource(dev, res[3]);
  2084. +
  2085.     if (!xrx200_switch_membase || !xrx200_mdio_membase ||
  2086.             !xrx200_mii_membase || !xrx200_pmac_membase) {
  2087. -       dev_err(&pdev->dev, "failed to request and remap io ranges \n");
  2088. +       dev_err(dev, "failed to request and remap io ranges \n");
  2089.         return -ENOMEM;
  2090.     }
  2091.  
  2092. -   of_for_each_phandle(&it, err, pdev->dev.of_node, "lantiq,phys", NULL, 0) {
  2093. +   of_for_each_phandle(&it, err, dev->of_node, "lantiq,phys", NULL, 0) {
  2094.         phy_np = it.node;
  2095.         if (phy_np) {
  2096.             struct platform_device *phy = of_find_device_by_node(phy_np);
  2097. -  
  2098. +
  2099.             of_node_put(phy_np);
  2100.             if (!platform_get_drvdata(phy))
  2101.                 return -EPROBE_DEFER;
  2102.         }
  2103.     }
  2104.  
  2105. +//TODO ? devm_clk_get
  2106.     /* get the clock */
  2107. -   xrx200_hw.clk = clk_get(&pdev->dev, NULL);
  2108. -   if (IS_ERR(xrx200_hw.clk)) {
  2109. -       dev_err(&pdev->dev, "failed to get clock\n");
  2110. -       return PTR_ERR(xrx200_hw.clk);
  2111. +   priv->clk = clk_get(dev, NULL);
  2112. +   if (IS_ERR(priv->clk)) {
  2113. +       dev_err(dev, "failed to get clock\n");
  2114. +       return PTR_ERR(priv->clk);
  2115.     }
  2116.  
  2117.     /* bring up the dma engine and IP core */
  2118. -   xrx200_dma_init(&pdev->dev, &xrx200_hw);
  2119. -   xrx200_hw_init(&xrx200_hw);
  2120. -   tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX]);
  2121. -   tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX_2].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX_2]);
  2122. +   err = xrx200_dma_init(priv);
  2123. +   if (err)
  2124. +       return err;
  2125. +
  2126. +   /* enable clock gate */
  2127. +   err = clk_prepare_enable(priv->clk);
  2128. +   if (err)
  2129. +       goto err_uninit_dma;
  2130. +
  2131. +   xrx200_hw_init(priv);
  2132. +
  2133. +   /* set wan port mask */
  2134. +   ltq_pmac_w32(priv->wan_map, PMAC_EWAN);
  2135. +
  2136. +
  2137. +   /* global dummy netdev for napi, for all DMA rings */
  2138. +   init_dummy_netdev(&priv->dummy_net);
  2139. +
  2140. +   /* setup NAPI */
  2141. +   for (i = 0; i < MAX_RX_RINGS; i++) {
  2142. +       netif_napi_add(&priv->dummy_net, &priv->rx[i].napi,
  2143. +                  xrx200_poll_rx, 32); //32 TODO value by number of queues?
  2144. +   }
  2145. +
  2146. +   for (i = 0; i < MAX_TX_RINGS; i++) {
  2147. +       netif_tx_napi_add(&priv->dummy_net, &priv->tx[i].napi,
  2148. +                 xrx200_tx_housekeeping, 48);  //TODO number by queues?
  2149. +   }
  2150.  
  2151.     /* bring up the mdio bus */
  2152. -   mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
  2153. +   mdio_np = of_find_compatible_node(dev->of_node, NULL,
  2154.                 "lantiq,xrx200-mdio");
  2155.     if (mdio_np)
  2156. -       if (xrx200_of_mdio(&xrx200_hw, mdio_np))
  2157. -           dev_err(&pdev->dev, "mdio probe failed\n");
  2158. +       if (xrx200_of_mdio(priv, mdio_np))
  2159. +           dev_err(dev, "mdio probe failed\n");    //TODO fail path?
  2160. +
  2161. +   INIT_LIST_HEAD(&priv->ifaces);
  2162.  
  2163.     /* load the interfaces */
  2164. -   for_each_child_of_node(pdev->dev.of_node, iface_np)
  2165. -       if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
  2166. -           if (xrx200_hw.num_devs < XRX200_MAX_DEV)
  2167. -               xrx200_of_iface(&xrx200_hw, iface_np, &pdev->dev);
  2168. -           else
  2169. -               dev_err(&pdev->dev,
  2170. -                   "only %d interfaces allowed\n",
  2171. -                   XRX200_MAX_DEV);
  2172. -       }
  2173. +   for_each_child_of_node(dev->of_node, iface_np)
  2174. +           if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
  2175. +               err = xrx200_of_iface(priv, iface_np, dev);
  2176. +
  2177. +               if (err) {
  2178. +                   //printk?
  2179. +                   goto err_unprepare_clk;
  2180. +               }
  2181. +           }
  2182.  
  2183. -   if (!xrx200_hw.num_devs) {
  2184. -       xrx200_hw_cleanup(&xrx200_hw);
  2185. -       dev_err(&pdev->dev, "failed to load interfaces\n");
  2186. -       return -ENOENT;
  2187. +#ifndef SW_POLLING
  2188. +//TODO this is sort of ugly, but original way seems to be weird
  2189. +//double register fills (once for Sw and second for WAN into MDIO_CLK_CFG0)
  2190. +//RFC if one can RMW MDIO_CLK_CFG0 after setting MDIO_CLK_CFG1, it could be split
  2191. +//and put back to xrx200_init
  2192. +//TODO maybe put before xrx200_of_iface
  2193. +   reg = 0;
  2194. +
  2195. +   list_for_each(pos, &priv->ifaces) {
  2196. +       struct list_head *port_list;
  2197. +       struct xrx200_iface *iface = list_entry(pos,
  2198. +                           struct xrx200_iface,
  2199. +                           iface);
  2200. +
  2201. +       list_for_each(port_list, &iface->ports) {
  2202. +           struct xrx200_port *port =
  2203. +               list_entry(port_list,
  2204. +                      struct xrx200_port,
  2205. +                      port);;
  2206. +
  2207. +           reg |= BIT(port->num);
  2208. +       }
  2209.     }
  2210.  
  2211. -   xrx200sw_init(&xrx200_hw);
  2212. +   ltq_mdio_w32(reg, MDIO_CLK_CFG0);
  2213. +   ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
  2214. +#endif
  2215.  
  2216. -   /* set wan port mask */
  2217. -   ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
  2218. +   platform_set_drvdata(pdev, priv);
  2219.  
  2220. -   for (i = 0; i < xrx200_hw.num_devs; i++) {
  2221. -       xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
  2222. -       xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
  2223. -       xrx200_hw.chan[XRX200_DMA_TX_2].devs[i] = xrx200_hw.devs[i];
  2224. -   }
  2225. +   return 0;
  2226.  
  2227. -   /* setup NAPI */
  2228. -   init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev);
  2229. -   netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev,
  2230. -           &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32);
  2231. +err_unprepare_clk:
  2232. +//TODO split for fail inside xrx200_of_iface, unregister_netdevs from list
  2233. +   clk_disable_unprepare(priv->clk);
  2234.  
  2235. -   platform_set_drvdata(pdev, &xrx200_hw);
  2236. +err_uninit_dma:
  2237. +//TODO rename to xrx200_dma_cleanup? maybe...
  2238. +   xrx200_hw_cleanup(priv);
  2239.  
  2240. -   return 0;
  2241. +   return err;
  2242.  }
  2243.  
  2244.  static int xrx200_remove(struct platform_device *pdev)
  2245.  {
  2246. -   struct net_device *dev = platform_get_drvdata(pdev);
  2247. -   struct xrx200_priv *priv;
  2248. +   int i;
  2249. +   struct xrx200_priv *priv = platform_get_drvdata(pdev);
  2250. +   struct xrx200_iface *iface;
  2251. +   struct list_head *pos;
  2252.  
  2253. -   if (!dev)
  2254. -       return 0;
  2255. +   /* free stack related instances */
  2256. +   list_for_each(pos, &priv->ifaces) {
  2257. +       iface = list_entry(pos, struct xrx200_iface, iface);
  2258.  
  2259. -   priv = netdev_priv(dev);
  2260. +       netif_tx_stop_all_queues(iface->net_dev);
  2261. +   }
  2262.  
  2263. -   /* free stack related instances */
  2264. -   netif_stop_queue(dev);
  2265. -   netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi);
  2266. +   for (i = 0; i < MAX_TX_RINGS; i++) {
  2267. +       netif_napi_del(&priv->tx[i].napi);
  2268. +   }
  2269.  
  2270. -   /* shut down hardware */
  2271. -   xrx200_hw_cleanup(&xrx200_hw);
  2272. +   for (i = 0; i < MAX_RX_RINGS; i++) {
  2273. +       netif_napi_del(&priv->rx[i].napi);
  2274. +   }
  2275.  
  2276.     /* remove the actual device */
  2277. -   unregister_netdev(dev);
  2278. -   free_netdev(dev);
  2279. +   list_for_each(pos, &priv->ifaces) {
  2280. +       iface = list_entry(pos, struct xrx200_iface, iface);
  2281. +
  2282. +       unregister_netdev(iface->net_dev);
  2283. +   }
  2284. +
  2285. +   /* release the clock */
  2286. +   clk_disable_unprepare(priv->clk);
  2287. +
  2288. +   /* shut down hardware */
  2289. +   xrx200_hw_cleanup(priv);
  2290.  
  2291.     return 0;
  2292.  }
  2293. --- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h 2019-08-06 19:06:58.000000000 +0200
  2294. +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h 2019-08-13 07:02:09.801309128 +0200
  2295. @@ -19,7 +19,7 @@
  2296.  #define LTQ_DMA_H__
  2297.  
  2298.  #define LTQ_DESC_SIZE      0x08    /* each descriptor is 64bit */
  2299. -#define LTQ_DESC_NUM       0x40    /* 64 descriptors / channel */
  2300. +#define LTQ_DESC_NUM       0x80    /* 128 descriptors / channel */
  2301.  
  2302.  #define LTQ_DMA_OWN        BIT(31) /* owner bit */
  2303.  #define LTQ_DMA_C      BIT(30) /* complete bit */
  2304. --- a/arch/mips/lantiq/xway/dma.c   2019-08-06 19:06:58.000000000 +0200
  2305. +++ b/arch/mips/lantiq/xway/dma.c   2019-08-13 07:03:54.169004352 +0200
  2306. @@ -49,7 +49,10 @@
  2307.  #define DMA_IRQ_ACK        0x7e        /* IRQ status register */
  2308.  #define DMA_POLL       BIT(31)     /* turn on channel polling */
  2309.  #define DMA_CLK_DIV4       BIT(6)      /* polling clock divider */
  2310. -#define DMA_2W_BURST       BIT(1)      /* 2 word burst length */
  2311. +#define DMA_1W_BURST       0x0     /* 1 word burst length/no burst */
  2312. +#define DMA_2W_BURST       0x1     /* 2 word burst length */
  2313. +#define DMA_4W_BURST       0x2     /* 4 word burst length */
  2314. +#define DMA_8W_BURST       0x3     /* 8 word burst length */
  2315.  #define DMA_MAX_CHANNEL        20      /* the soc has 20 channels */
  2316.  #define DMA_ETOP_ENDIANNESS    (0xf << 8) /* endianness swap etop channels */
  2317.  #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
  2318. @@ -137,7 +140,7 @@
  2319.     spin_lock_irqsave(&ltq_dma_lock, flags);
  2320.     ltq_dma_w32(ch->nr, LTQ_DMA_CS);
  2321.     ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
  2322. -   ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
  2323. +   ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);   //0xff mask
  2324.     ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
  2325.     wmb();
  2326.     ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
  2327. @@ -154,7 +157,13 @@
  2328.     ltq_dma_alloc(ch);
  2329.  
  2330.     spin_lock_irqsave(&ltq_dma_lock, flags);
  2331. -   ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
  2332. +
  2333. +//DMA_DESCPT BIT(3) //end of descriptor
  2334. +//BIT(1)   //end of packet
  2335. +// ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
  2336. +   ltq_dma_w32(BIT(1), LTQ_DMA_CIE);
  2337. +  
  2338. +  
  2339.     ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
  2340.     ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
  2341.     spin_unlock_irqrestore(&ltq_dma_lock, flags);
  2342. @@ -193,6 +202,12 @@
  2343.     ltq_dma_w32(p, LTQ_DMA_PS);
  2344.     switch (p) {
  2345.     case DMA_PORT_ETOP:
  2346. +
  2347. +       /* 8 words burst, data must be aligned on 4*N bytes or freeze */
  2348. +//TODO? different bursts for TX and RX (RX is fine at 1G eth)     
  2349. +       ltq_dma_w32_mask(0x3c, (DMA_8W_BURST << 4) | (DMA_8W_BURST << 2),
  2350. +           LTQ_DMA_PCTRL);
  2351. +
  2352.         /*
  2353.          * Tell the DMA engine to swap the endianness of data frames and
  2354.          * drop packets if the channel arbitration fails.
  2355. @@ -240,10 +255,18 @@
  2356.     for (i = 0; i < DMA_MAX_CHANNEL; i++) {
  2357.         ltq_dma_w32(i, LTQ_DMA_CS);
  2358.         ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
  2359. -       ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
  2360.         ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
  2361.     }
  2362.  
  2363. +//TODO 0x100 << 4 fastest TX without fragments
  2364. +// 0x100 for fragments timeouts, 0x10 only under really _heavy_ load
  2365. +//TODO not dependent on channel select (LTQ_DMA_CS), why it was in for cycle
  2366. +   ltq_dma_w32(DMA_POLL | (0x10 << 4), LTQ_DMA_CPOLL);
  2367. +
  2368. +//TODO packet arbitration ???, test different values
  2369. +//0x3ff << 16 multiple burst count, 1<<30 multiple burst arbitration, 1<<31 packet arbitration, 1<<0 reset (!)
  2370. +// ltq_dma_w32((1 << 31) | 0x40000, LTQ_DMA_CTRL);
  2371. +
  2372.     id = ltq_dma_r32(LTQ_DMA_ID);
  2373.     dev_info(&pdev->dev,
  2374.         "Init done - hw rev: %X, ports: %d, channels: %d\n",
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