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- Clock Information:
- ------------------
- -----------------------------------+------------------------+-------+
- Clock Signal | Clock buffer(FF name) | Load |
- -----------------------------------+------------------------+-------+
- clock | XLXI_2:CLK0 | 91 |
- clock | XLXI_2:CLKFX | 18 |
- -----------------------------------+------------------------+-------+
- Asynchronous Control Signals Information:
- ----------------------------------------
- No asynchronous control signals found in this design
- Timing Summary:
- ---------------
- Speed Grade: -4
- Minimum period: 48.018ns (Maximum Frequency: 20.826MHz)
- Minimum input arrival time before clock: 2.756ns
- Maximum output required time after clock: 6.005ns
- Maximum combinational path delay: No path found
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