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May 27th, 2019
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  1. Clock Information:
  2. ------------------
  3. -----------------------------------+------------------------+-------+
  4. Clock Signal | Clock buffer(FF name) | Load |
  5. -----------------------------------+------------------------+-------+
  6. clock | XLXI_2:CLK0 | 91 |
  7. clock | XLXI_2:CLKFX | 18 |
  8. -----------------------------------+------------------------+-------+
  9.  
  10. Asynchronous Control Signals Information:
  11. ----------------------------------------
  12. No asynchronous control signals found in this design
  13.  
  14. Timing Summary:
  15. ---------------
  16. Speed Grade: -4
  17.  
  18. Minimum period: 48.018ns (Maximum Frequency: 20.826MHz)
  19. Minimum input arrival time before clock: 2.756ns
  20. Maximum output required time after clock: 6.005ns
  21. Maximum combinational path delay: No path found
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