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-- Company:
-- Engineer:
--
-- Create Date: 10/23/2019 05:12:14 PM
-- Design Name:
-- Module Name: carry_lookahead_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity carry_lookahead_adder is
    generic ( n : integer := 4);
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end carry_lookahead_adder;

architecture Behavioral of carry_lookahead_adder is

signal c : std_logic_vector(4 downto 0);
signal g : std_logic_vector(3 downto 0);
signal p : std_logic_vector(3 downto 0);

component fulAdder1 iS
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Cin : in STD_LOGIC;
           S : out STD_LOGIC;
           Cout : out STD_LOGIC);
end component;
signal carry_out: std_logic_vector(N downto 0);

begin

fullA: FOR k IN 0 to N-1 GENERATE
ca: fulAdder1
 port map ( A(K), B(K),carry_out(k), s(k), carry_out(k+1));
end GENERATE fullA;

carry_out(0) <= cin;
cout <= carry_out(N);


process (a, b, c, g, p, c)
begin
	c(0) <= cin;
	for i in 0 to 3 loop
		g(i) <= a(i) and b(i);
		p(i) <= a(i) or b(i);
		c(i + 1) <= g(i) or (p(i) and c(i));
	end loop;
	cout <= c(4);
end process;

end Behavioral;