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# THIS IS A WIZARD-GENERATED FILE.
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# Version 11.0 Build 157 04/27/2011 SJ Web Edition
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# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
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# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
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# Clock constraints

create_clock -name CLOCK_50 -period 10.000 [get_keepers {CLOCK_50}]


# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
set_false_path -from [get_clocks {CLOCK_50}] -to [get_ports {GPIO_0[2] GPIO_0[3]}]


# Automatically calculate clock uncertainty to jitter and other effects.
#derive_clock_uncertainty
# Not supported for family Cyclone II

# tsu/th constraints

# tco constraints

# tpd constraints