module top (
	input  wire sync,
	output wire valid,
	output wire armed,
	input  wire clk
);

	reg       samp_sync;
    reg [2:0] samp_cnt;
	reg       samp_valid;

    always @(posedge clk)
        if (samp_sync)
            samp_cnt <= 3'b101;
        else
          case (samp_cnt)
              3'b000:  samp_cnt <= 3'b011;
              3'b001:  samp_cnt <= 3'b000;
              3'b010:  samp_cnt <= 3'b001;
              3'b011:  samp_cnt <= 3'b010;
              3'b100:  samp_cnt <= 3'b011;
              3'b101:  samp_cnt <= 3'b100;
              3'b110:  samp_cnt <= 3'b101;
              3'b111:  samp_cnt <= 3'b110;
              default: samp_cnt <= 3'bxxx;
          endcase

	always @(posedge clk)
	begin
		samp_sync  <= sync;
		samp_valid <= (samp_cnt[1:0] == 2'b10) & ~samp_valid;
	end

	assign valid = samp_valid;
    assign armed = samp_cnt[2];

endmodule