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Nov 22nd, 2017
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  1. Timing constraint: PATH filter = FROM TIMEGRP "filter_from" TO TIMEGRP "filter_to"
  2. 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
  3. 0 timing errors detected. (0 setup errors, 0 hold errors)
  4. Maximum delay is 7.556ns.
  5. --------------------------------------------------------------------------------
  6. Delay (setup path): 7.556ns (data path)
  7. Source: ddram_a_12 (FF)
  8. Destination: ddram_a<12> (PAD)
  9. Data Path Delay: 7.556ns (Levels of Logic = 1)
  10.  
  11. Maximum Data Path at Slow Process Corner: ddram_a_12 to ddram_a<12>
  12. Location Delay type Delay(ns) Physical Resource
  13. Logical Resource(s)
  14. ------------------------------------------------- -------------------
  15. G6.O net (fanout=1) 4.874 ddram_a_12
  16. G6.PAD Tioop 2.682 ddram_a<12>
  17. ddram_a_12_OBUF
  18. ddram_a<12>
  19. ------------------------------------------------- ---------------------------
  20. Total 7.556ns (2.682ns logic, 4.874ns route)
  21. (35.5% logic, 64.5% route)
  22.  
  23. --------------------------------------------------------------------------------
  24.  
  25. Delay (setup path): 5.945ns (data path)
  26. Source: ddram_a_0 (FF)
  27. Destination: ddram_a<0> (PAD)
  28. Data Path Delay: 5.945ns (Levels of Logic = 1)
  29.  
  30. Maximum Data Path at Slow Process Corner: ddram_a_0 to ddram_a<0>
  31. Location Delay type Delay(ns) Physical Resource
  32. Logical Resource(s)
  33. ------------------------------------------------- -------------------
  34. J7.O net (fanout=1) 3.263 ddram_a_0
  35. J7.PAD Tioop 2.682 ddram_a<0>
  36. ddram_a_0_OBUF
  37. ddram_a<0>
  38. ------------------------------------------------- ---------------------------
  39. Total 5.945ns (2.682ns logic, 3.263ns route)
  40. (45.1% logic, 54.9% route)
  41.  
  42. --------------------------------------------------------------------------------
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