lpc55s36.cfg

source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME lpc55s36
}

#
# JTAG mode TAP
#
if { [info exists M33_JTAG_TAPID] } {
	set _JTAG_TAPID $M33_JTAG_TAPID
} else {
	set _JTAG_TAPID 0x4ba00477
}

#
# SWD mode TAP
#
if { [info exists M33_SWD_TAPID] } {
	set _SWD_TAPID $M33_SWD_TAPID
} else {
#	set _SWD_TAPID 0x2ba01477
	set _SWD_TAPID 0x0be12477
	#set _SWD_TAPID 0x410fd214
}

if { [using_jtag] } {
	set _CPUTAPID $_JTAG_TAPID
} {
	set _CPUTAPID $_SWD_TAPID
}

swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
				-expected-id $_CPUTAPID
dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap

# LPCSSS36-EVK has 112 KB SRAM
if { [info exists WORKAREASIZE] } {
	set _WORKAREASIZE $WORKAREASIZE
} else {
	set _WORKAREASIZE 0x1C000
}
$_CHIPNAME.m4 configure -work-area-phys 0x20000000 \
			-work-area-size $_WORKAREASIZE -work-area-backup 0

set _TARGETNAME $_CHIPNAME.m4
#target create $_TARGETNAME cortex_m -dap $_CHIPNAME.m4.dap

set _FLASHNAME $_CHIPNAME.flash

#flash bank $_CHIPNAME.flash lpc2000 0 0 0 0 $_TARGETNAME
flash bank $_FLASHNAME lpc2000 0 0 0 0 $_TARGETNAME auto 100000 calc_checksum

#if {![using_hla]} {
#   # on this CPU we should use VECTRESET to perform a soft reset and
#   # manually reset the periphery
#   # SRST or SYSRESETREQ disable the debug interface for the time of
#   # the reset and will not fit our requirements for a consistent debug
#   # session
#   cortex_m reset_config vectreset
#}

#cortex_m reset_config sysresetreq
adapter speed 1000

#adapter srst delay 100
#adapter srst pulse_width 100
#reset_config  srst_nogate

# reset_config srst_only