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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x02>;
  5. model = "ZynqMP ZCU208 RevA";
  6. #size-cells = <0x02>;
  7. compatible = "xlnx,zynqmp-zcu208-revA\0xlnx,zynqmp-zcu208\0xlnx,zynqmp";
  8.  
  9. ref48M {
  10. #clock-cells = <0x00>;
  11. clock-frequency = <0x2dc6c00>;
  12. compatible = "fixed-clock";
  13. phandle = <0x1c>;
  14. };
  15.  
  16. fclk3 {
  17. clocks = <0x04 0x4a>;
  18. compatible = "xlnx,fclk";
  19. status = "okay";
  20. phandle = <0x9e>;
  21. };
  22.  
  23. ina226-dac-avcc {
  24. io-channels = <0x35 0x00 0x35 0x01 0x35 0x02 0x35 0x03>;
  25. compatible = "iio-hwmon";
  26. };
  27.  
  28. fclk1 {
  29. clocks = <0x04 0x48>;
  30. compatible = "xlnx,fclk";
  31. status = "okay";
  32. phandle = <0x9c>;
  33. };
  34.  
  35. memory@0 {
  36. device_type = "memory";
  37. reg = <0x00 0x00 0x00 0x7ff00000 0x08 0x00 0x00 0x80000000>;
  38. };
  39.  
  40. ina226-dac-avtt {
  41. io-channels = <0x31 0x00 0x31 0x01 0x31 0x02 0x31 0x03>;
  42. compatible = "iio-hwmon";
  43. };
  44.  
  45. ina226-mgt1v8 {
  46. io-channels = <0x2f 0x00 0x2f 0x01 0x2f 0x02 0x2f 0x03>;
  47. compatible = "iio-hwmon";
  48. };
  49.  
  50. apu_axi_1@a8000000 {
  51. reg = <0x00 0xa8000000 0x00 0x8000000>;
  52. phandle = <0xa0>;
  53. };
  54.  
  55. pss_ref_clk {
  56. u-boot,dm-pre-reloc;
  57. #clock-cells = <0x00>;
  58. clock-frequency = <0x1fca055>;
  59. compatible = "fixed-clock";
  60. phandle = <0x0b>;
  61. };
  62.  
  63. ina226-vcc1v2 {
  64. io-channels = <0x2b 0x00 0x2b 0x01 0x2b 0x02 0x2b 0x03>;
  65. compatible = "iio-hwmon";
  66. };
  67.  
  68. dp_aclk {
  69. clock-accuracy = <0x64>;
  70. #clock-cells = <0x00>;
  71. clock-frequency = <0x5f5e100>;
  72. compatible = "fixed-clock";
  73. phandle = <0x24>;
  74. };
  75.  
  76. bootcount@0 {
  77. i2c-eeprom = <0x36>;
  78. offset = <0x40>;
  79. compatible = "u-boot,bootcount-i2c-eeprom";
  80. phandle = <0xa1>;
  81. };
  82.  
  83. ina226-mgtavcc {
  84. io-channels = <0x2d 0x00 0x2d 0x01 0x2d 0x02 0x2d 0x03>;
  85. compatible = "iio-hwmon";
  86. };
  87.  
  88. gt_crx_ref_clk {
  89. u-boot,dm-pre-reloc;
  90. #clock-cells = <0x00>;
  91. clock-frequency = <0x66ff300>;
  92. compatible = "fixed-clock";
  93. phandle = <0x0f>;
  94. };
  95.  
  96. ina226-dac-avccaux {
  97. io-channels = <0x32 0x00 0x32 0x01 0x32 0x02 0x32 0x03>;
  98. compatible = "iio-hwmon";
  99. };
  100.  
  101. leds {
  102. compatible = "gpio-leds";
  103.  
  104. heartbeat_led {
  105. linux,default-trigger = "heartbeat";
  106. label = "heartbeat";
  107. gpios = <0x19 0x17 0x00>;
  108. };
  109. };
  110.  
  111. psci {
  112. method = "smc";
  113. compatible = "arm,psci-0.2";
  114. };
  115.  
  116. ina226-vccint-io-bram-ps {
  117. io-channels = <0x29 0x00 0x29 0x01 0x29 0x02 0x29 0x03>;
  118. compatible = "iio-hwmon";
  119. };
  120.  
  121. dcc {
  122. u-boot,dm-pre-reloc;
  123. compatible = "arm,dcc";
  124. status = "okay";
  125. phandle = <0x38>;
  126. };
  127.  
  128. ina226-mgt1v2 {
  129. io-channels = <0x2e 0x00 0x2e 0x01 0x2e 0x02 0x2e 0x03>;
  130. compatible = "iio-hwmon";
  131. };
  132.  
  133. gpio-keys {
  134. autorepeat;
  135. compatible = "gpio-keys";
  136.  
  137. sw19 {
  138. autorepeat;
  139. wakeup-source;
  140. label = "sw19";
  141. linux,code = <0x6c>;
  142. gpios = <0x19 0x16 0x00>;
  143. };
  144. };
  145.  
  146. edac {
  147. compatible = "arm,cortex-a53-edac";
  148. };
  149.  
  150. ina226-vccint-ams {
  151. io-channels = <0x30 0x00 0x30 0x01 0x30 0x02 0x30 0x03>;
  152. compatible = "iio-hwmon";
  153. };
  154.  
  155. fpga-full {
  156. fpga-mgr = <0x10>;
  157. #address-cells = <0x02>;
  158. firmware-name = "qps-fpga.bit.bin";
  159. resets = <0x13 0x74>;
  160. uid = <0x923123f>;
  161. #size-cells = <0x02>;
  162. compatible = "fpga-region";
  163. ranges;
  164. phandle = <0x4c>;
  165. pid = <0x00>;
  166. };
  167.  
  168. timer {
  169. interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
  170. interrupt-parent = <0x05>;
  171. compatible = "arm,armv8-timer";
  172. };
  173.  
  174. fclk2 {
  175. clocks = <0x04 0x49>;
  176. compatible = "xlnx,fclk";
  177. status = "okay";
  178. phandle = <0x9d>;
  179. };
  180.  
  181. opp-table-cpu {
  182. opp-shared;
  183. compatible = "operating-points-v2";
  184. phandle = <0x01>;
  185.  
  186. opp02 {
  187. opp-microvolt = <0xf4240>;
  188. opp-hz = <0x00 0x17d783fc>;
  189. clock-latency-ns = <0x7a120>;
  190. };
  191.  
  192. opp00 {
  193. opp-microvolt = <0xf4240>;
  194. opp-hz = <0x00 0x47868bf4>;
  195. clock-latency-ns = <0x7a120>;
  196. };
  197.  
  198. opp03 {
  199. opp-microvolt = <0xf4240>;
  200. opp-hz = <0x00 0x11e1a2fd>;
  201. clock-latency-ns = <0x7a120>;
  202. };
  203.  
  204. opp01 {
  205. opp-microvolt = <0xf4240>;
  206. opp-hz = <0x00 0x23c345fa>;
  207. clock-latency-ns = <0x7a120>;
  208. };
  209. };
  210.  
  211. aliases {
  212. ethernet0 = "/axi/ethernet@ff0e0000";
  213. i2c1 = "/axi/i2c@ff030000";
  214. spi0 = "/axi/spi@ff0f0000";
  215. nvmem0 = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54";
  216. rtc0 = "/axi/rtc@ffa60000";
  217. i2c0 = "/axi/i2c@ff020000";
  218. serial0 = "/axi/serial@ff000000";
  219. };
  220.  
  221. firmware {
  222.  
  223. zynqmp-firmware {
  224. method = "smc";
  225. u-boot,dm-pre-reloc;
  226. #power-domain-cells = <0x01>;
  227. compatible = "xlnx,zynqmp-firmware";
  228. phandle = <0x11>;
  229.  
  230. pinctrl {
  231. compatible = "xlnx,zynqmp-pinctrl";
  232. status = "okay";
  233. phandle = <0x4b>;
  234.  
  235. i2c1-default {
  236. phandle = <0x1a>;
  237.  
  238. mux {
  239. function = "i2c1";
  240. groups = "i2c1_4_grp";
  241. };
  242.  
  243. conf {
  244. slew-rate = <0x01>;
  245. bias-pull-up;
  246. groups = "i2c1_4_grp";
  247. power-source = <0x01>;
  248. };
  249. };
  250.  
  251. i2c1-gpio {
  252. phandle = <0x1b>;
  253.  
  254. mux {
  255. function = "gpio0";
  256. groups = "gpio0_16_grp\0gpio0_17_grp";
  257. };
  258.  
  259. conf {
  260. slew-rate = <0x01>;
  261. groups = "gpio0_16_grp\0gpio0_17_grp";
  262. power-source = <0x01>;
  263. };
  264. };
  265.  
  266. i2c0-gpio {
  267. phandle = <0x18>;
  268.  
  269. mux {
  270. function = "gpio0";
  271. groups = "gpio0_14_grp\0gpio0_15_grp";
  272. };
  273.  
  274. conf {
  275. slew-rate = <0x01>;
  276. groups = "gpio0_14_grp\0gpio0_15_grp";
  277. power-source = <0x01>;
  278. };
  279. };
  280.  
  281. i2c0-default {
  282. phandle = <0x17>;
  283.  
  284. mux {
  285. function = "i2c0";
  286. groups = "i2c0_3_grp";
  287. };
  288.  
  289. conf {
  290. slew-rate = <0x01>;
  291. bias-pull-up;
  292. groups = "i2c0_3_grp";
  293. power-source = <0x01>;
  294. };
  295. };
  296. };
  297.  
  298. pcap {
  299. clock-names = "ref_clk";
  300. clocks = <0x04 0x29>;
  301. compatible = "xlnx,zynqmp-pcap-fpga";
  302. phandle = <0x10>;
  303. };
  304.  
  305. gpio {
  306. gpio-controller;
  307. compatible = "xlnx,zynqmp-gpio-modepin";
  308. phandle = <0x21>;
  309. #gpio-cells = <0x02>;
  310. };
  311.  
  312. nvmem_firmware {
  313. #address-cells = <0x01>;
  314. #size-cells = <0x01>;
  315. compatible = "xlnx,zynqmp-nvmem-fw";
  316.  
  317. efuse_pufmisc@54 {
  318. reg = <0x54 0x04>;
  319. phandle = <0x46>;
  320. };
  321.  
  322. efuse_ppk1hash@d0 {
  323. reg = <0xd0 0x30>;
  324. phandle = <0x4a>;
  325. };
  326.  
  327. efuse_usr3@2c {
  328. reg = <0x2c 0x04>;
  329. phandle = <0x3f>;
  330. };
  331.  
  332. efuse_dna@c {
  333. reg = <0x0c 0x0c>;
  334. phandle = <0x3b>;
  335. };
  336.  
  337. efuse_ppk0hash@a0 {
  338. reg = <0xa0 0x30>;
  339. phandle = <0x49>;
  340. };
  341.  
  342. efuse_usr1@24 {
  343. reg = <0x24 0x04>;
  344. phandle = <0x3d>;
  345. };
  346.  
  347. efuse_usr6@38 {
  348. reg = <0x38 0x04>;
  349. phandle = <0x42>;
  350. };
  351.  
  352. efuse_spkid@5c {
  353. reg = <0x5c 0x04>;
  354. phandle = <0x48>;
  355. };
  356.  
  357. efuse_chash@50 {
  358. reg = <0x50 0x04>;
  359. phandle = <0x45>;
  360. };
  361.  
  362. efuse_usr4@30 {
  363. reg = <0x30 0x04>;
  364. phandle = <0x40>;
  365. };
  366.  
  367. efuse_miscusr@40 {
  368. reg = <0x40 0x04>;
  369. phandle = <0x44>;
  370. };
  371.  
  372. efuse_usr7@3c {
  373. reg = <0x3c 0x04>;
  374. phandle = <0x43>;
  375. };
  376.  
  377. efuse_usr2@28 {
  378. reg = <0x28 0x04>;
  379. phandle = <0x3e>;
  380. };
  381.  
  382. efuse_usr0@20 {
  383. reg = <0x20 0x04>;
  384. phandle = <0x3c>;
  385. };
  386.  
  387. soc_revision@0 {
  388. reg = <0x00 0x04>;
  389. phandle = <0x3a>;
  390. };
  391.  
  392. efuse_sec@58 {
  393. reg = <0x58 0x04>;
  394. phandle = <0x47>;
  395. };
  396.  
  397. efuse_usr5@34 {
  398. reg = <0x34 0x04>;
  399. phandle = <0x41>;
  400. };
  401. };
  402.  
  403. zynqmp-power {
  404. u-boot,dm-pre-reloc;
  405. interrupts = <0x00 0x23 0x04>;
  406. interrupt-parent = <0x05>;
  407. compatible = "xlnx,zynqmp-power";
  408. phandle = <0x39>;
  409. mboxes = <0x0a 0x00 0x0a 0x01>;
  410. mbox-names = "tx\0rx";
  411. };
  412.  
  413. clock-controller {
  414. clock-names = "pss_ref_clk\0video_clk\0pss_alt_ref_clk\0aux_ref_clk\0gt_crx_ref_clk";
  415. u-boot,dm-pre-reloc;
  416. clocks = <0x0b 0x0c 0x0d 0x0e 0x0f>;
  417. #clock-cells = <0x01>;
  418. compatible = "xlnx,zynqmp-clk";
  419. phandle = <0x04>;
  420. };
  421.  
  422. reset-controller {
  423. #reset-cells = <0x01>;
  424. compatible = "xlnx,zynqmp-reset";
  425. phandle = <0x13>;
  426. };
  427. };
  428. };
  429.  
  430. fclk0 {
  431. clocks = <0x04 0x47>;
  432. compatible = "xlnx,fclk";
  433. status = "okay";
  434. phandle = <0x9b>;
  435. };
  436.  
  437. pss_alt_ref_clk {
  438. u-boot,dm-pre-reloc;
  439. #clock-cells = <0x00>;
  440. clock-frequency = <0x00>;
  441. compatible = "fixed-clock";
  442. phandle = <0x0d>;
  443. };
  444.  
  445. aux_ref_clk {
  446. u-boot,dm-pre-reloc;
  447. #clock-cells = <0x00>;
  448. clock-frequency = <0x19bfcc0>;
  449. compatible = "fixed-clock";
  450. phandle = <0x0e>;
  451. };
  452.  
  453. chosen {
  454. u-boot,version = "2023.01";
  455. xlnx,eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54";
  456. u-boot,bootcount-device = "/bootcount@0";
  457. bootargs = "root=/dev/mmcblk0p2 panic=5 init=/sbin/preinit";
  458. stdout-path = "serial0:115200n8";
  459. };
  460.  
  461. ina226-vadj-fmc {
  462. io-channels = <0x2c 0x00 0x2c 0x01 0x2c 0x02 0x2c 0x03>;
  463. compatible = "iio-hwmon";
  464. };
  465.  
  466. ina226-adc-avcc {
  467. io-channels = <0x33 0x00 0x33 0x01 0x33 0x02 0x33 0x03>;
  468. compatible = "iio-hwmon";
  469. };
  470.  
  471. zynqmp_ipi {
  472. #address-cells = <0x02>;
  473. xlnx,ipi-id = <0x00>;
  474. u-boot,dm-pre-reloc;
  475. interrupts = <0x00 0x23 0x04>;
  476. #size-cells = <0x02>;
  477. interrupt-parent = <0x05>;
  478. compatible = "xlnx,zynqmp-ipi-mailbox";
  479. ranges;
  480. phandle = <0x37>;
  481.  
  482. mailbox@ff9905c0 {
  483. xlnx,ipi-id = <0x04>;
  484. reg-names = "local_request_region\0local_response_region\0remote_request_region\0remote_response_region";
  485. u-boot,dm-pre-reloc;
  486. #mbox-cells = <0x01>;
  487. reg = <0x00 0xff9905c0 0x00 0x20 0x00 0xff9905e0 0x00 0x20 0x00 0xff990e80 0x00 0x20 0x00 0xff990ea0 0x00 0x20>;
  488. phandle = <0x0a>;
  489. };
  490. };
  491.  
  492. video_clk {
  493. u-boot,dm-pre-reloc;
  494. #clock-cells = <0x00>;
  495. clock-frequency = <0x19bfcc0>;
  496. compatible = "fixed-clock";
  497. phandle = <0x0c>;
  498. };
  499.  
  500. ina226-adc-avccaux {
  501. io-channels = <0x34 0x00 0x34 0x01 0x34 0x02 0x34 0x03>;
  502. compatible = "iio-hwmon";
  503. };
  504.  
  505. apu_axi_0@a0080000 {
  506. reg = <0x00 0xa0080000 0x00 0x40000>;
  507. phandle = <0x9f>;
  508. };
  509.  
  510. pmu {
  511. interrupt-affinity = <0x06 0x07 0x08 0x09>;
  512. interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04>;
  513. interrupt-parent = <0x05>;
  514. compatible = "arm,armv8-pmuv3";
  515. };
  516.  
  517. cpus {
  518. #address-cells = <0x01>;
  519. #size-cells = <0x00>;
  520.  
  521. cpu@1 {
  522. cpu-idle-states = <0x02>;
  523. device_type = "cpu";
  524. compatible = "arm,cortex-a53";
  525. next-level-cache = <0x03>;
  526. reg = <0x01>;
  527. enable-method = "psci";
  528. phandle = <0x07>;
  529. operating-points-v2 = <0x01>;
  530. };
  531.  
  532. l2-cache {
  533. cache-level = <0x02>;
  534. compatible = "cache";
  535. phandle = <0x03>;
  536. };
  537.  
  538. idle-states {
  539. entry-method = "psci";
  540.  
  541. cpu-sleep-0 {
  542. entry-latency-us = <0x12c>;
  543. local-timer-stop;
  544. exit-latency-us = <0x258>;
  545. arm,psci-suspend-param = <0x40000000>;
  546. compatible = "arm,idle-state";
  547. phandle = <0x02>;
  548. min-residency-us = <0x2710>;
  549. };
  550. };
  551.  
  552. cpu@2 {
  553. cpu-idle-states = <0x02>;
  554. device_type = "cpu";
  555. compatible = "arm,cortex-a53";
  556. next-level-cache = <0x03>;
  557. reg = <0x02>;
  558. enable-method = "psci";
  559. phandle = <0x08>;
  560. operating-points-v2 = <0x01>;
  561. };
  562.  
  563. cpu@0 {
  564. clocks = <0x04 0x0a>;
  565. cpu-idle-states = <0x02>;
  566. device_type = "cpu";
  567. compatible = "arm,cortex-a53";
  568. next-level-cache = <0x03>;
  569. reg = <0x00>;
  570. enable-method = "psci";
  571. phandle = <0x06>;
  572. operating-points-v2 = <0x01>;
  573. };
  574.  
  575. cpu@3 {
  576. cpu-idle-states = <0x02>;
  577. device_type = "cpu";
  578. compatible = "arm,cortex-a53";
  579. next-level-cache = <0x03>;
  580. reg = <0x03>;
  581. enable-method = "psci";
  582. phandle = <0x09>;
  583. operating-points-v2 = <0x01>;
  584. };
  585. };
  586.  
  587. __symbols__ {
  588. efuse_usr0 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr0@20";
  589. fpd_dma_chan3 = "/axi/dma-controller@fd520000";
  590. mdio = "/axi/ethernet@ff0e0000/mdio";
  591. i2c_si570_user_c1 = "/axi/i2c@ff030000/i2c-mux@75/i2c@1";
  592. efuse_ppk0hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk0hash@a0";
  593. ams_ps = "/axi/ams@ffa50000/ams_ps@0";
  594. vadj_fmc = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@45";
  595. i2c_8a34001 = "/axi/i2c@ff030000/i2c-mux@74/i2c@4";
  596. nand0 = "/axi/nand-controller@ff100000";
  597. fclk3 = "/fclk3";
  598. si570_3 = "/axi/i2c@ff030000/i2c-mux@75/i2c@1/clock-generator@5d";
  599. zynqmp_pcap = "/firmware/zynqmp-firmware/pcap";
  600. reserved = "/reserved-memory/buffer@0";
  601. CPU_SLEEP_0 = "/cpus/idle-states/cpu-sleep-0";
  602. efuse_chash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_chash@50";
  603. ipi_mailbox_pmu1 = "/zynqmp_ipi/mailbox@ff9905c0";
  604. i2c1 = "/axi/i2c@ff030000";
  605. vccint_ams = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@49";
  606. fpd_dma_chan1 = "/axi/dma-controller@fd500000";
  607. bootcount = "/bootcount@0";
  608. i2c_clk104 = "/axi/i2c@ff030000/i2c-mux@74/i2c@5";
  609. efuse_sec = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_sec@58";
  610. i2c_si5341 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1";
  611. si5341_2 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@2";
  612. ttc3 = "/axi/timer@ff140000";
  613. qspi = "/axi/spi@ff0f0000";
  614. zynqmp_dp_snd_pcm0 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm0";
  615. fclk1 = "/fclk1";
  616. dac_avcc = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4e";
  617. gpu = "/axi/gpu@fd4b0000";
  618. spi0 = "/axi/spi@ff040000";
  619. mgtavcc = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@46";
  620. si570_1 = "/axi/i2c@ff030000/i2c-mux@74/i2c@2/clock-generator@5d";
  621. lpd_dma_chan8 = "/axi/dma-controller@ffaf0000";
  622. pinctrl_i2c1_default = "/firmware/zynqmp-firmware/pinctrl/i2c1-default";
  623. efuse_usr7 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr7@3c";
  624. mgt1v8 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@48";
  625. gpio = "/axi/gpio@ff0a0000";
  626. dac_avtt = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4a";
  627. zynqmp_clk = "/firmware/zynqmp-firmware/clock-controller";
  628. usb1 = "/axi/usb@ff9e0000";
  629. ttc1 = "/axi/timer@ff120000";
  630. amba = "/axi";
  631. adc_avccaux = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4d";
  632. efuse_spkid = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_spkid@5c";
  633. pss_ref_clk = "/pss_ref_clk";
  634. vcc1v2 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@43";
  635. lpd_dma_chan6 = "/axi/dma-controller@ffad0000";
  636. efuse_usr5 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr5@34";
  637. fpd_dma_chan8 = "/axi/dma-controller@fd570000";
  638. efuse_ppk1hash = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_ppk1hash@d0";
  639. clocking0 = "/axi/clocking0";
  640. rfip = "/axi/usp_rf_data_converter@a0000000";
  641. si5341_9 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@9";
  642. gem3 = "/axi/ethernet@ff0e0000";
  643. dp_aclk = "/dp_aclk";
  644. apu_axi_11 = "/apu_axi_1@a8000000";
  645. cpu3 = "/cpus/cpu@3";
  646. zynqmp_dpaud_setting = "/axi/dp_aud@fd4ac000";
  647. dwc3_0 = "/axi/usb@ff9d0000/usb@fe200000";
  648. perf_monitor_cci = "/axi/perf-monitor@fd490000";
  649. lpd_dma_chan4 = "/axi/dma-controller@ffab0000";
  650. efuse_usr3 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr3@2c";
  651. fpd_dma_chan6 = "/axi/dma-controller@fd550000";
  652. gt_crx_ref_clk = "/gt_crx_ref_clk";
  653. gic = "/axi/interrupt-controller@f9010000";
  654. misc_clk_0 = "/axi/misc_clk_0";
  655. gem1 = "/axi/ethernet@ff0c0000";
  656. sata = "/axi/ahci@fd0c0000";
  657. irps5401_45 = "/axi/i2c@ff020000/i2c-mux@75/i2c@2/irps5401@45";
  658. cpu1 = "/cpus/cpu@1";
  659. xilinx_ams = "/axi/ams@ffa50000";
  660. perf_monitor_lpd = "/axi/perf-monitor@ffa10000";
  661. uart0 = "/axi/serial@ff000000";
  662. zynqmp_dp_snd_codec0 = "/axi/display@fd4a0000/zynqmp_dp_snd_codec0";
  663. dcc = "/dcc";
  664. lpd_dma_chan2 = "/axi/dma-controller@ffa90000";
  665. ams_pl = "/axi/ams@ffa50000/ams_pl@400";
  666. L2 = "/cpus/l2-cache";
  667. efuse_usr1 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr1@24";
  668. fpd_dma_chan4 = "/axi/dma-controller@fd530000";
  669. cci = "/axi/cci@fd6e0000";
  670. mgt1v2 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@47";
  671. axi_gpio_spi_mux = "/axi/gpio@a0205000";
  672. si5341_5 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@5";
  673. perf_monitor_ddr = "/axi/perf-monitor@fd0b0000";
  674. cpu_opp_table = "/opp-table-cpu";
  675. mac_address = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54/mac-address@23";
  676. can0 = "/axi/can@ff060000";
  677. pcie = "/axi/pcie@fd0e0000";
  678. sdhci0 = "/axi/mmc@ff160000";
  679. perf_monitor_ocm = "/axi/perf-monitor@ffa00000";
  680. watchdog0 = "/axi/watchdog@fd4d0000";
  681. fpga_full = "/fpga-full";
  682. fpd_dma_chan2 = "/axi/dma-controller@fd510000";
  683. i2c_si570_user_c0 = "/axi/i2c@ff030000/i2c-mux@74/i2c@2";
  684. si5341_3 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@3";
  685. zynqmp_firmware = "/firmware/zynqmp-firmware";
  686. zynqmp_dp_snd_pcm1 = "/axi/display@fd4a0000/zynqmp_dp_snd_pcm1";
  687. fclk2 = "/fclk2";
  688. pinctrl_i2c0_default = "/firmware/zynqmp-firmware/pinctrl/i2c0-default";
  689. spi1 = "/axi/spi@ff050000";
  690. si570_2 = "/axi/i2c@ff030000/i2c-mux@74/i2c@3/clock-generator@5d";
  691. axi_dma_0 = "/axi/dma@a1000000";
  692. ocm = "/axi/memory-controller@ff960000";
  693. pinctrl_i2c1_gpio = "/firmware/zynqmp-firmware/pinctrl/i2c1-gpio";
  694. eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0/eeprom@54";
  695. i2c0 = "/axi/i2c@ff020000";
  696. ttc2 = "/axi/timer@ff130000";
  697. soc_revision = "/firmware/zynqmp-firmware/nvmem_firmware/soc_revision@0";
  698. fclk0 = "/fclk0";
  699. pss_alt_ref_clk = "/pss_alt_ref_clk";
  700. lpd_dma_chan7 = "/axi/dma-controller@ffae0000";
  701. efuse_usr6 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr6@38";
  702. efuse_dna = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_dna@c";
  703. aux_ref_clk = "/aux_ref_clk";
  704. clocking1 = "/axi/clocking1";
  705. psgtr = "/axi/phy@fd400000";
  706. vccint_io_bram_ps = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@41";
  707. idt_8a34001 = "/axi/i2c@ff030000/i2c-mux@74/i2c@4/phc@5b";
  708. usb0 = "/axi/usb@ff9d0000";
  709. si5341 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36";
  710. ttc0 = "/axi/timer@ff110000";
  711. flash0 = "/axi/spi@ff0f0000/flash@0";
  712. mc = "/axi/memory-controller@fd070000";
  713. dac_avccaux = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4b";
  714. zynqmp_dpsub = "/axi/display@fd4a0000";
  715. ref48 = "/ref48M";
  716. pinctrl0 = "/firmware/zynqmp-firmware/pinctrl";
  717. pinctrl_i2c0_gpio = "/firmware/zynqmp-firmware/pinctrl/i2c0-gpio";
  718. dwc3_1 = "/axi/usb@ff9e0000/usb@fe300000";
  719. afi0 = "/axi/afi0";
  720. phy0 = "/axi/ethernet@ff0e0000/mdio/ethernet-phy@c";
  721. lpd_dma_chan5 = "/axi/dma-controller@ffac0000";
  722. zynqmp_ipi = "/zynqmp_ipi";
  723. tca6416_u15 = "/axi/i2c@ff020000/gpio@20";
  724. efuse_usr4 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr4@30";
  725. fpd_dma_chan7 = "/axi/dma-controller@fd560000";
  726. video_clk = "/video_clk";
  727. adc_avcc = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@4c";
  728. gem2 = "/axi/ethernet@ff0d0000";
  729. vccint = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@40";
  730. efuse_pufmisc = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_pufmisc@54";
  731. zynqmp_dpdma = "/axi/dma-controller@fd4c0000";
  732. cpu2 = "/cpus/cpu@2";
  733. uart1 = "/axi/serial@ff010000";
  734. efuse_miscusr = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_miscusr@40";
  735. apu_axi_00 = "/apu_axi_0@a0080000";
  736. lpd_dma_chan3 = "/axi/dma-controller@ffaa0000";
  737. efuse_usr2 = "/firmware/zynqmp-firmware/nvmem_firmware/efuse_usr2@28";
  738. fpd_dma_chan5 = "/axi/dma-controller@fd540000";
  739. si5341_6 = "/axi/i2c@ff030000/i2c-mux@74/i2c@1/clock-generator@36/out@6";
  740. zynqmp_dp_snd_card0 = "/axi/display@fd4a0000/zynqmp_dp_snd_card";
  741. zynqmp_power = "/firmware/zynqmp-firmware/zynqmp-power";
  742. can1 = "/axi/can@ff070000";
  743. gem0 = "/axi/ethernet@ff0b0000";
  744. pcie_intc = "/axi/pcie@fd0e0000/legacy-interrupt-controller";
  745. sdhci1 = "/axi/mmc@ff170000";
  746. irps5401_44 = "/axi/i2c@ff020000/i2c-mux@75/i2c@2/irps5401@44";
  747. rtc = "/axi/rtc@ffa60000";
  748. smmu = "/axi/smmu@fd800000";
  749. lpd_watchdog = "/axi/watchdog@ff150000";
  750. vcc1v8 = "/axi/i2c@ff020000/i2c-mux@75/i2c@0/ina226@42";
  751. modepin_gpio = "/firmware/zynqmp-firmware/gpio";
  752. cpu0 = "/cpus/cpu@0";
  753. zynqmp_reset = "/firmware/zynqmp-firmware/reset-controller";
  754. i2c_si570_mgt = "/axi/i2c@ff030000/i2c-mux@74/i2c@3";
  755. i2c_eeprom = "/axi/i2c@ff030000/i2c-mux@74/i2c@0";
  756. lpd_dma_chan1 = "/axi/dma-controller@ffa80000";
  757. };
  758.  
  759. ina226-vccint {
  760. io-channels = <0x28 0x00 0x28 0x01 0x28 0x02 0x28 0x03>;
  761. compatible = "iio-hwmon";
  762. };
  763.  
  764. reserved-memory {
  765. #address-cells = <0x02>;
  766. #size-cells = <0x02>;
  767. ranges;
  768.  
  769. buffer@0 {
  770. reg = <0x00 0x7c000000 0x00 0x4000000>;
  771. phandle = <0xa2>;
  772. no-map;
  773. };
  774. };
  775.  
  776. axi {
  777. #address-cells = <0x02>;
  778. u-boot,dm-pre-reloc;
  779. #size-cells = <0x02>;
  780. compatible = "simple-bus";
  781. ranges;
  782. phandle = <0x4d>;
  783.  
  784. memory-controller@ff960000 {
  785. interrupts = <0x00 0x0a 0x04>;
  786. interrupt-parent = <0x05>;
  787. compatible = "xlnx,zynqmp-ocmc-1.0";
  788. reg = <0x00 0xff960000 0x00 0x1000>;
  789. phandle = <0x7d>;
  790. };
  791.  
  792. timer@ff140000 {
  793. power-domains = <0x11 0x1b>;
  794. timer-width = <0x20>;
  795. interrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04>;
  796. clocks = <0x04 0x1f>;
  797. interrupt-parent = <0x05>;
  798. compatible = "cdns,ttc";
  799. status = "okay";
  800. reg = <0x00 0xff140000 0x00 0x1000>;
  801. phandle = <0x8d>;
  802. };
  803.  
  804. spi@ff050000 {
  805. power-domains = <0x11 0x24>;
  806. #address-cells = <0x01>;
  807. clock-names = "ref_clk\0pclk";
  808. interrupts = <0x00 0x14 0x04>;
  809. clocks = <0x04 0x3b 0x04 0x1f>;
  810. #size-cells = <0x00>;
  811. interrupt-parent = <0x05>;
  812. compatible = "cdns,spi-r1p6";
  813. status = "disabled";
  814. reg = <0x00 0xff050000 0x00 0x1000>;
  815. phandle = <0x89>;
  816. };
  817.  
  818. rtc@ffa60000 {
  819. calibration = <0x7fff>;
  820. interrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>;
  821. interrupt-parent = <0x05>;
  822. compatible = "xlnx,zynqmp-rtc";
  823. status = "okay";
  824. interrupt-names = "alarm\0sec";
  825. reg = <0x00 0xffa60000 0x00 0x100>;
  826. phandle = <0x84>;
  827. };
  828.  
  829. ethernet@ff0e0000 {
  830. power-domains = <0x11 0x20>;
  831. iommus = <0x12 0x877>;
  832. #address-cells = <0x01>;
  833. phy-mode = "rgmii-id";
  834. nvmem-cells = <0x15>;
  835. clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
  836. local-mac-address = [76 1b db 1f 78 12];
  837. resets = <0x13 0x20>;
  838. interrupts = <0x00 0x3f 0x04 0x00 0x3f 0x04>;
  839. clocks = <0x04 0x1f 0x04 0x6b 0x04 0x30 0x04 0x34 0x04 0x2c>;
  840. #size-cells = <0x00>;
  841. interrupt-parent = <0x05>;
  842. compatible = "xlnx,zynqmp-gem\0cdns,gem";
  843. status = "okay";
  844. nvmem-cell-names = "mac-address";
  845. reg = <0x00 0xff0e0000 0x00 0x1000>;
  846. phandle = <0x67>;
  847. phy-handle = <0x14>;
  848. reset-names = "gem3_rst";
  849. xlnx,ptp-enet-clock = <0x00>;
  850.  
  851. mdio {
  852. #address-cells = <0x01>;
  853. #size-cells = <0x00>;
  854. phandle = <0x68>;
  855.  
  856. ethernet-phy@c {
  857. ti,dp83867-rxctrl-strap-quirk;
  858. ti,tx-internal-delay = <0x0a>;
  859. #phy-cells = <0x01>;
  860. reset-gpios = <0x16 0x06 0x01>;
  861. compatible = "ethernet-phy-id2000.a231";
  862. ti,fifo-depth = <0x01>;
  863. ti,rx-internal-delay = <0x08>;
  864. reg = <0x0c>;
  865. phandle = <0x14>;
  866. };
  867. };
  868. };
  869.  
  870. dma-controller@ffab0000 {
  871. power-domains = <0x11 0x2b>;
  872. clock-names = "clk_main\0clk_apb";
  873. interrupts = <0x00 0x50 0x04>;
  874. clocks = <0x04 0x44 0x04 0x1f>;
  875. interrupt-parent = <0x05>;
  876. xlnx,bus-width = <0x40>;
  877. compatible = "xlnx,zynqmp-dma-1.0";
  878. status = "okay";
  879. reg = <0x00 0xffab0000 0x00 0x1000>;
  880. phandle = <0x5d>;
  881. #dma-cells = <0x01>;
  882. };
  883.  
  884. dp_aud@fd4ac000 {
  885. compatible = "xlnx,zynqmp-dpaud-setting\0syscon";
  886. reg = <0x00 0xfd4ac000 0x00 0x1000>;
  887. phandle = <0x22>;
  888. };
  889.  
  890. ams@ffa50000 {
  891. #address-cells = <0x01>;
  892. reg-names = "ams-base";
  893. interrupts = <0x00 0x38 0x04>;
  894. clocks = <0x04 0x46>;
  895. #io-channel-cells = <0x01>;
  896. #size-cells = <0x01>;
  897. interrupt-parent = <0x05>;
  898. compatible = "xlnx,zynqmp-ams";
  899. ranges = <0x00 0x00 0xffa50800 0x800>;
  900. status = "okay";
  901. interrupt-names = "ams-irq";
  902. reg = <0x00 0xffa50000 0x00 0x800>;
  903. phandle = <0x96>;
  904.  
  905. ams_pl@400 {
  906. compatible = "xlnx,zynqmp-ams-pl";
  907. status = "okay";
  908. reg = <0x400 0x400>;
  909. phandle = <0x98>;
  910. };
  911.  
  912. ams_ps@0 {
  913. compatible = "xlnx,zynqmp-ams-ps";
  914. status = "okay";
  915. reg = <0x00 0x400>;
  916. phandle = <0x97>;
  917. };
  918. };
  919.  
  920. usp_rf_data_converter@a0000000 {
  921. param-list = <0x00 0xa0 0x00 0x1000000 0x00 0x00 0x1000000 0x1000000 0x2000000 0x1000000 0x1000000 0x1000000 0x691d554d 0x10750f40 0xb81e85eb 0x51b86e40 0xb81e85eb 0x51b87e40 0x30000000 0x3000000 0x1000000 0x00 0x00 0x1c40 0x2000000 0x1000000 0x1000000 0x00 0x2000000 0x00 0x00 0x00 0x2000000 0x00 0x1000000 0x00 0x2000000 0x00 0x00 0x00 0x2000000 0x00 0x00 0x8000000 0x1000000 0x00 0x00 0x1000000 0x00 0x10000000 0x00 0x00 0x00 0x3000000 0x00 0x8000000 0x1000000 0x00 0x00 0x1000000 0x00 0x10000000 0x00 0x00 0x00 0x3000000 0x1000000 0x1000000 0xfd6ff39 0xcc971740 0xb81e85eb 0x51b86e40 0xb81e85eb 0x51b87e40 0x30000000 0x2000000 0x1000000 0x00 0x00 0x1c40 0x2000000 0x00 0x1000000 0x00 0x00 0x00 0x00 0x00 0x2000000 0x00 0x1000000 0x00 0x00 0x00 0x00 0x00 0x2000000 0x00 0x00 0x2000000 0xc000000 0x00 0x00 0x2000000 0x00 0x10000000 0x00 0x00 0x00 0x3000000 0x00 0x2000000 0xc000000 0x00 0x00 0x2000000 0x00 0x10000000 0x00 0x00 0x00 0x3000000 0x1000000 0x1000000 0x691d554d 0x10750f40 0xb81e85eb 0x51b86e40 0xb81e85eb 0x51b87e40 0x30000000 0x3000000 0x1000000 0x00 0x00 0x1c40 0x2000000 0x1000000 0x1000000 0x00 0x2000000 0x00 0x00 0x00 0x2000000 0x00 0x1000000 0x00 0x2000000 0x00 0x00 0x00 0x2000000 0x00 0x00 0x8000000 0x1000000 0x00 0x00 0x1000000 0x00 0x10000000 0x00 0x00 0x00 0x3000000 0x00 0x8000000 0x1000000 0x00 0x00 0x1000000 0x00 0x10000000 0x00 0x00 0x00 0x3000000 0x1000000 0x1000000 0xfd6ff39 0xcc971740 0xb81e85eb 0x51b86e40 0xb81e85eb 0x51b87e40 0x30000000 0x2000000 0x1000000 0x00 0x00 0x1c40 0x2000000 0x00 0x1000000 0x00 0x00 0x00 0x00 0x00 0x2000000 0x00 0x1000000 0x00 0x00 0x00 0x00 0x00 0x2000000 0x00 0x00 0x2000000 0xc000000 0x00 0x00 0x2000000 0x00 0x10000000 0x00 0x00 0x00 0x3000000 0x00 0x2000000 0xc000000 0x00 0x00 0x2000000 0x00 0x10000000 0x00 0x00 0x00 0x3000000 0x1000000 0x1000000 0x61325530 0x2aa90340 0xb81e85eb 0x51b86e40 0xb81e85eb 0x51b87e40 0x28000000 0x4000000 0x1000000 0x00 0x00 0x1440 0x2000000 0x1000000 0x00 0x1000000 0x00 0x00 0x2000000 0x00 0x2000000 0x1000000 0x1000000 0x5000000 0x00 0x2000000 0x1000000 0x1000000 0x5000000 0x00 0x2000000 0x00 0x8000000 0x00 0x00 0x3000000 0x00 0x8000000 0x00 0x00 0x3000000 0x1000000 0x1000000 0x61325530 0x2aa90340 0xb81e85eb 0x51b86e40 0xb81e85eb 0x51b87e40 0x28000000 0x4000000 0x1000000 0x00 0x00 0x1440 0x2000000 0x1000000 0x00 0x1000000 0x00 0x00 0x2000000 0x00 0x2000000 0x1000000 0x1000000 0x5000000 0x00 0x2000000 0x1000000 0x1000000 0x5000000 0x00 0x2000000 0x00 0x8000000 0x00 0x00 0x3000000 0x00 0x8000000 0x00 0x00 0x3000000 0x1000000 0x1000000 0x61325530 0x2aa90340 0xb81e85eb 0x51b86e40 0xb81e85eb 0x51b87e40 0x28000000 0x4000000 0x1000000 0x00 0x00 0x1440 0x2000000 0x1000000 0x00 0x1000000 0x00 0x00 0x2000000 0x00 0x2000000 0x1000000 0x1000000 0x5000000 0x00 0x2000000 0x1000000 0x1000000 0x5000000 0x00 0x2000000 0x00 0x8000000 0x00 0x00 0x3000000 0x00 0x8000000 0x00 0x00 0x3000000 0x1000000 0x1000000 0x61325530 0x2aa90340 0xb81e85eb 0x51b86e40 0xb81e85eb 0x51b87e40 0x28000000 0x4000000 0x1000000 0x00 0x00 0x1440 0x2000000 0x1000000 0x00 0x1000000 0x00 0x00 0x2000000 0x00 0x2000000 0x1000000 0x1000000 0x5000000 0x00 0x2000000 0x1000000 0x1000000 0x5000000 0x00 0x2000000 0x00 0x8000000 0x00 0x00 0x3000000 0x00 0x8000000 0x00 0x00 0x3000000>;
  922. clock-names = "s_axi_aclk\0m0_axis_aclk\0m1_axis_aclk\0m2_axis_aclk\0m3_axis_aclk\0s0_axis_aclk\0s1_axis_aclk\0s2_axis_aclk\0s3_axis_aclk";
  923. interrupts = <0x00 0x59 0x04>;
  924. clocks = <0x04 0x47 0xa4 0xa4 0xa4 0xa4 0xa4 0xa4 0xa4 0xa4>;
  925. interrupt-parent = <0x05>;
  926. compatible = "xlnx,usp-rf-data-converter-2.6";
  927. num-insts = <0x01>;
  928. interrupt-names = "irq";
  929. reg = <0x00 0xa0000000 0x00 0x40000>;
  930. phandle = <0xaa>;
  931. };
  932.  
  933. memory-controller@fd070000 {
  934. interrupts = <0x00 0x70 0x04>;
  935. interrupt-parent = <0x05>;
  936. compatible = "xlnx,zynqmp-ddrc-2.40a";
  937. reg = <0x00 0xfd070000 0x00 0x30000>;
  938. phandle = <0x62>;
  939. };
  940.  
  941. mmc@ff170000 {
  942. power-domains = <0x11 0x28>;
  943. iommus = <0x12 0x871>;
  944. clock-output-names = "clk_out_sd1\0clk_in_sd1";
  945. xlnx,mio-bank = <0x01>;
  946. clock-names = "clk_xin\0clk_ahb";
  947. assigned-clocks = <0x04 0x37>;
  948. u-boot,dm-pre-reloc;
  949. resets = <0x13 0x27>;
  950. interrupts = <0x00 0x31 0x04>;
  951. clocks = <0x04 0x37 0x04 0x1f>;
  952. #clock-cells = <0x01>;
  953. interrupt-parent = <0x05>;
  954. clock-frequency = <0xb2cfe8b>;
  955. no-1-8-v;
  956. compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a";
  957. status = "okay";
  958. disable-wp;
  959. reg = <0x00 0xff170000 0x00 0x1000>;
  960. phandle = <0x87>;
  961. };
  962.  
  963. dma-controller@ffaf0000 {
  964. power-domains = <0x11 0x2b>;
  965. clock-names = "clk_main\0clk_apb";
  966. interrupts = <0x00 0x54 0x04>;
  967. clocks = <0x04 0x44 0x04 0x1f>;
  968. interrupt-parent = <0x05>;
  969. xlnx,bus-width = <0x40>;
  970. compatible = "xlnx,zynqmp-dma-1.0";
  971. status = "okay";
  972. reg = <0x00 0xffaf0000 0x00 0x1000>;
  973. phandle = <0x61>;
  974. #dma-cells = <0x01>;
  975. };
  976.  
  977. perf-monitor@fd0b0000 {
  978. xlnx,metric-count-width = <0x20>;
  979. xlnx,have-sampled-metric-cnt = <0x01>;
  980. xlnx,enable-trace = <0x00>;
  981. xlnx,global-count-width = <0x20>;
  982. xlnx,enable-event-count = <0x01>;
  983. interrupts = <0x00 0x7b 0x04>;
  984. clocks = <0x04 0x1c>;
  985. xlnx,enable-profile = <0x00>;
  986. xlnx,metric-count-scale = <0x01>;
  987. interrupt-parent = <0x05>;
  988. xlnx,num-monitor-slots = <0x06>;
  989. compatible = "xlnx,axi-perf-monitor";
  990. xlnx,num-of-counters = <0x0a>;
  991. reg = <0x00 0xfd0b0000 0x00 0x10000>;
  992. phandle = <0x7f>;
  993. xlnx,metrics-sample-count-width = <0x20>;
  994. xlnx,enable-event-log = <0x00>;
  995. };
  996.  
  997. dma-controller@fd510000 {
  998. power-domains = <0x11 0x2a>;
  999. iommus = <0x12 0x14e9>;
  1000. clock-names = "clk_main\0clk_apb";
  1001. interrupts = <0x00 0x7d 0x04>;
  1002. clocks = <0x04 0x13 0x04 0x1f>;
  1003. interrupt-parent = <0x05>;
  1004. xlnx,bus-width = <0x80>;
  1005. compatible = "xlnx,zynqmp-dma-1.0";
  1006. status = "okay";
  1007. reg = <0x00 0xfd510000 0x00 0x1000>;
  1008. phandle = <0x52>;
  1009. #dma-cells = <0x01>;
  1010. };
  1011.  
  1012. dma-controller@ffa80000 {
  1013. power-domains = <0x11 0x2b>;
  1014. clock-names = "clk_main\0clk_apb";
  1015. interrupts = <0x00 0x4d 0x04>;
  1016. clocks = <0x04 0x44 0x04 0x1f>;
  1017. interrupt-parent = <0x05>;
  1018. xlnx,bus-width = <0x40>;
  1019. compatible = "xlnx,zynqmp-dma-1.0";
  1020. status = "okay";
  1021. reg = <0x00 0xffa80000 0x00 0x1000>;
  1022. phandle = <0x5a>;
  1023. #dma-cells = <0x01>;
  1024. };
  1025.  
  1026. nand-controller@ff100000 {
  1027. power-domains = <0x11 0x2c>;
  1028. iommus = <0x12 0x872>;
  1029. #address-cells = <0x01>;
  1030. clock-names = "controller\0bus";
  1031. interrupts = <0x00 0x0e 0x04>;
  1032. clocks = <0x04 0x3c 0x04 0x1f>;
  1033. #size-cells = <0x00>;
  1034. interrupt-parent = <0x05>;
  1035. compatible = "xlnx,zynqmp-nand-controller\0arasan,nfc-v3p10";
  1036. status = "disabled";
  1037. reg = <0x00 0xff100000 0x00 0x1000>;
  1038. phandle = <0x63>;
  1039. };
  1040.  
  1041. dma-controller@fd550000 {
  1042. power-domains = <0x11 0x2a>;
  1043. iommus = <0x12 0x14ed>;
  1044. clock-names = "clk_main\0clk_apb";
  1045. interrupts = <0x00 0x81 0x04>;
  1046. clocks = <0x04 0x13 0x04 0x1f>;
  1047. interrupt-parent = <0x05>;
  1048. xlnx,bus-width = <0x80>;
  1049. compatible = "xlnx,zynqmp-dma-1.0";
  1050. status = "okay";
  1051. reg = <0x00 0xfd550000 0x00 0x1000>;
  1052. phandle = <0x56>;
  1053. #dma-cells = <0x01>;
  1054. };
  1055.  
  1056. interrupt-controller@f9010000 {
  1057. num_cpus = <0x02>;
  1058. interrupts = <0x01 0x09 0xf04>;
  1059. interrupt-parent = <0x05>;
  1060. compatible = "arm,gic-400";
  1061. #interrupt-cells = <0x03>;
  1062. num_interrupts = <0x60>;
  1063. reg = <0x00 0xf9010000 0x00 0x10000 0x00 0xf9020000 0x00 0x20000 0x00 0xf9040000 0x00 0x20000 0x00 0xf9060000 0x00 0x20000>;
  1064. phandle = <0x05>;
  1065. interrupt-controller;
  1066. };
  1067.  
  1068. timer@ff110000 {
  1069. power-domains = <0x11 0x18>;
  1070. timer-width = <0x20>;
  1071. interrupts = <0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04>;
  1072. clocks = <0x04 0x1f>;
  1073. interrupt-parent = <0x05>;
  1074. compatible = "cdns,ttc";
  1075. status = "okay";
  1076. reg = <0x00 0xff110000 0x00 0x1000>;
  1077. phandle = <0x8a>;
  1078. };
  1079.  
  1080. ethernet@ff0b0000 {
  1081. power-domains = <0x11 0x1d>;
  1082. iommus = <0x12 0x874>;
  1083. #address-cells = <0x01>;
  1084. clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
  1085. resets = <0x13 0x1d>;
  1086. interrupts = <0x00 0x39 0x04 0x00 0x39 0x04>;
  1087. clocks = <0x04 0x1f 0x04 0x68 0x04 0x2d 0x04 0x31 0x04 0x2c>;
  1088. #size-cells = <0x00>;
  1089. interrupt-parent = <0x05>;
  1090. compatible = "xlnx,zynqmp-gem\0cdns,gem";
  1091. status = "disabled";
  1092. reg = <0x00 0xff0b0000 0x00 0x1000>;
  1093. phandle = <0x64>;
  1094. reset-names = "gem0_rst";
  1095. };
  1096.  
  1097. clocking0 {
  1098. clock-output-names = "fabric_clk";
  1099. assigned-clocks = <0x04 0x47>;
  1100. assigned-clock-rates = <0x5f5dd19>;
  1101. clocks = <0x04 0x47>;
  1102. #clock-cells = <0x00>;
  1103. compatible = "xlnx,fclk";
  1104. phandle = <0xa6>;
  1105. };
  1106.  
  1107. usb@ff9d0000 {
  1108. power-domains = <0x11 0x16>;
  1109. xlnx,tz-nonsecure = <0x01>;
  1110. #address-cells = <0x02>;
  1111. xlnx,usb-reset-mode = <0x00>;
  1112. phy-names = "usb3-phy";
  1113. clock-names = "bus_clk\0ref_clk";
  1114. assigned-clocks = <0x04 0x20 0x04 0x22>;
  1115. resets = <0x13 0x3b 0x13 0x3d 0x13 0x3f>;
  1116. clocks = <0x04 0x20 0x04 0x22>;
  1117. #size-cells = <0x02>;
  1118. xlnx,usb-polarity = <0x00>;
  1119. reset-gpios = <0x21 0x01 0x01>;
  1120. compatible = "xlnx,zynqmp-dwc3";
  1121. ranges;
  1122. status = "okay";
  1123. phys = <0x20 0x02 0x04 0x00 0x02>;
  1124. reg = <0x00 0xff9d0000 0x00 0x100>;
  1125. phandle = <0x90>;
  1126. reset-names = "usb_crst\0usb_hibrst\0usb_apbrst";
  1127.  
  1128. usb@fe200000 {
  1129. iommus = <0x12 0x860>;
  1130. snps,resume-hs-terminations;
  1131. snps,quirk-frame-length-adjustment = <0x20>;
  1132. clock-names = "ref";
  1133. snps,usb3_lpm_capable;
  1134. interrupts = <0x00 0x41 0x04 0x00 0x45 0x04 0x00 0x4b 0x04>;
  1135. clocks = <0x04 0x22>;
  1136. interrupt-parent = <0x05>;
  1137. compatible = "snps,dwc3";
  1138. status = "okay";
  1139. interrupt-names = "dwc_usb3\0otg\0hiber";
  1140. snps,enable_guctl1_ipd_quirk;
  1141. reg = <0x00 0xfe200000 0x00 0x40000>;
  1142. phandle = <0x91>;
  1143. dr_mode = "host";
  1144. maximum-speed = "super-speed";
  1145. snps,enable_guctl1_resume_quirk;
  1146. };
  1147. };
  1148.  
  1149. dma-controller@fd4c0000 {
  1150. power-domains = <0x11 0x29>;
  1151. iommus = <0x12 0xce4>;
  1152. clock-names = "axi_clk";
  1153. assigned-clocks = <0x04 0x14>;
  1154. interrupts = <0x00 0x7a 0x04>;
  1155. clocks = <0x04 0x14>;
  1156. interrupt-parent = <0x05>;
  1157. compatible = "xlnx,zynqmp-dpdma";
  1158. status = "disabled";
  1159. reg = <0x00 0xfd4c0000 0x00 0x1000>;
  1160. phandle = <0x23>;
  1161. dma-channels = <0x06>;
  1162. #dma-cells = <0x01>;
  1163. };
  1164.  
  1165. dma-controller@ffac0000 {
  1166. power-domains = <0x11 0x2b>;
  1167. clock-names = "clk_main\0clk_apb";
  1168. interrupts = <0x00 0x51 0x04>;
  1169. clocks = <0x04 0x44 0x04 0x1f>;
  1170. interrupt-parent = <0x05>;
  1171. xlnx,bus-width = <0x40>;
  1172. compatible = "xlnx,zynqmp-dma-1.0";
  1173. status = "okay";
  1174. reg = <0x00 0xffac0000 0x00 0x1000>;
  1175. phandle = <0x5e>;
  1176. #dma-cells = <0x01>;
  1177. };
  1178.  
  1179. gpio@ff0a0000 {
  1180. power-domains = <0x11 0x2e>;
  1181. gpio-mask-low = <0x5600>;
  1182. gpio-controller;
  1183. gpio-line-names = "QSPI_LWR_CLK\0QSPI_LWR_DQ1\0QSPI_LWR_DQ2\0QSPI_LWR_DQ3\0QSPI_LWR_DQ0\0QSPI_LWR_CS_B\0\0QSPI_UPR_CS_B\0QSPI_UPR_DQ0\0QSPI_UPR_DQ1\0QSPI_UPR_DQ2\0QSPI_UPR_DQ3\0QSPI_UPR_CLK\0PS_GPIO2\0I2C0_SCL\0I2C0_SDA\0I2C1_SCL\0I2C1_SDA\0UART0_TXD\0UART0_RXD\0\0\0BUTTON\0LED\0\0\0PMU_INPUT\0\0\0\0\0\0PMU_GPO0\0PMU_GPO1\0PMU_GPO2\0PMU_GPO3\0PMU_GPO4\0PMU_GPO5\0PS_GPIO1\0SDIO_SEL\0SDIO_DIR_CMD\0SDIO_DIR_DAT0\0SDIO_DIR_DAT1\0\0\0SDIO_DETECT\0SDIO_DAT0\0SDIO_DAT1\0SDIO_DAT2\0SDIO_DAT3\0SDIO_CMD\0SDIO_CLK\0USB_CLK\0USB_DIR\0USB_DATA2\0USB_NXT\0USB_DATA0\0USB_DATA1\0USB_STP\0USB_DATA3\0USB_DATA4\0USB_DATA5\0USB_DATA6\0USB_DATA7\0ENET_TX_CLK\0ENET_TX_D0\0ENET_TX_D1\0ENET_TX_D2\0ENET_TX_D3\0ENET_TX_CTRL\0ENET_RX_CLK\0ENET_RX_D0\0ENET_RX_D1\0ENET_RX_D2\0ENET_RX_D3\0ENET_RX_CTRL\0ENET_MDC\0ENET_MDIO\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0";
  1184. interrupts = <0x00 0x10 0x04>;
  1185. clocks = <0x04 0x1f>;
  1186. gpio-mask-high = <0x00>;
  1187. interrupt-parent = <0x05>;
  1188. compatible = "xlnx,zynqmp-gpio-1.0";
  1189. #interrupt-cells = <0x02>;
  1190. status = "okay";
  1191. reg = <0x00 0xff0a0000 0x00 0x1000>;
  1192. phandle = <0x19>;
  1193. emio-gpio-width = <0x20>;
  1194. #gpio-cells = <0x02>;
  1195. interrupt-controller;
  1196. };
  1197.  
  1198. misc_clk_0 {
  1199. #clock-cells = <0x00>;
  1200. clock-frequency = <0x1d4c0000>;
  1201. compatible = "fixed-clock";
  1202. phandle = <0xa4>;
  1203. };
  1204.  
  1205. i2c@ff020000 {
  1206. power-domains = <0x11 0x25>;
  1207. pinctrl-names = "default\0gpio";
  1208. #address-cells = <0x01>;
  1209. pinctrl-0 = <0x17>;
  1210. interrupts = <0x00 0x11 0x04>;
  1211. clocks = <0x04 0x3d>;
  1212. #size-cells = <0x00>;
  1213. interrupt-parent = <0x05>;
  1214. clock-frequency = <0x61a80>;
  1215. compatible = "cdns,i2c-r1p14";
  1216. pinctrl-1 = <0x18>;
  1217. status = "okay";
  1218. reg = <0x00 0xff020000 0x00 0x1000>;
  1219. phandle = <0x69>;
  1220. scl-gpios = <0x19 0x0e 0x00>;
  1221. sda-gpios = <0x19 0x0f 0x00>;
  1222.  
  1223. gpio@20 {
  1224. gpio-controller;
  1225. gpio-line-names = "MAX6643_OT_B\0MAX6643_FANFAIL_B\0MIO26_PMU_INPUT_LS\0DAC_AVTT_VOUT_SEL\0\0IIC_MUX_RESET_B\0GEM3_EXP_RESET_B\0MAX6643_FULL_SPEED\0FMCP_HSPC_PRSNT_M2C_B\0\0\0VCCINT_VRHOT_B\0\08A34001_EXP_RST_B\0IRPS5401_ALERT_B\0INA226_PMBUS_ALERT";
  1226. compatible = "ti,tca6416";
  1227. reg = <0x20>;
  1228. phandle = <0x16>;
  1229. #gpio-cells = <0x02>;
  1230. };
  1231.  
  1232. i2c-mux@75 {
  1233. #address-cells = <0x01>;
  1234. #size-cells = <0x00>;
  1235. compatible = "nxp,pca9544";
  1236. reg = <0x75>;
  1237.  
  1238. i2c@0 {
  1239. #address-cells = <0x01>;
  1240. #size-cells = <0x00>;
  1241. reg = <0x00>;
  1242.  
  1243. ina226@47 {
  1244. #io-channel-cells = <0x01>;
  1245. label = "ina226-mgt1v2";
  1246. compatible = "ti,ina226";
  1247. reg = <0x47>;
  1248. phandle = <0x2e>;
  1249. shunt-resistor = <0x1388>;
  1250. };
  1251.  
  1252. ina226@4e {
  1253. #io-channel-cells = <0x01>;
  1254. label = "ina226-dac-avcc";
  1255. compatible = "ti,ina226";
  1256. reg = <0x4e>;
  1257. phandle = <0x35>;
  1258. shunt-resistor = <0x1388>;
  1259. };
  1260.  
  1261. ina226@45 {
  1262. #io-channel-cells = <0x01>;
  1263. label = "ina226-vadj-fmc";
  1264. compatible = "ti,ina226";
  1265. reg = <0x45>;
  1266. phandle = <0x2c>;
  1267. shunt-resistor = <0x1388>;
  1268. };
  1269.  
  1270. ina226@4c {
  1271. #io-channel-cells = <0x01>;
  1272. label = "ina226-adc-avcc";
  1273. compatible = "ti,ina226";
  1274. reg = <0x4c>;
  1275. phandle = <0x33>;
  1276. shunt-resistor = <0x1388>;
  1277. };
  1278.  
  1279. ina226@43 {
  1280. #io-channel-cells = <0x01>;
  1281. label = "ina226-vcc1v2";
  1282. compatible = "ti,ina226";
  1283. reg = <0x43>;
  1284. phandle = <0x2b>;
  1285. shunt-resistor = <0x1388>;
  1286. };
  1287.  
  1288. ina226@4a {
  1289. #io-channel-cells = <0x01>;
  1290. label = "ina226-dac-avtt";
  1291. compatible = "ti,ina226";
  1292. reg = <0x4a>;
  1293. phandle = <0x31>;
  1294. shunt-resistor = <0x1388>;
  1295. };
  1296.  
  1297. ina226@41 {
  1298. #io-channel-cells = <0x01>;
  1299. label = "ina226-vccint-io-bram-ps";
  1300. compatible = "ti,ina226";
  1301. reg = <0x41>;
  1302. phandle = <0x29>;
  1303. shunt-resistor = <0x1388>;
  1304. };
  1305.  
  1306. ina226@48 {
  1307. #io-channel-cells = <0x01>;
  1308. label = "ina226-mgt1v8";
  1309. compatible = "ti,ina226";
  1310. reg = <0x48>;
  1311. phandle = <0x2f>;
  1312. shunt-resistor = <0x1388>;
  1313. };
  1314.  
  1315. ina226@46 {
  1316. #io-channel-cells = <0x01>;
  1317. label = "ina226-mgtavcc";
  1318. compatible = "ti,ina226";
  1319. reg = <0x46>;
  1320. phandle = <0x2d>;
  1321. shunt-resistor = <0x7d0>;
  1322. };
  1323.  
  1324. ina226@4d {
  1325. #io-channel-cells = <0x01>;
  1326. label = "ina226-adc-avccaux";
  1327. compatible = "ti,ina226";
  1328. reg = <0x4d>;
  1329. phandle = <0x34>;
  1330. shunt-resistor = <0x1388>;
  1331. };
  1332.  
  1333. ina226@4b {
  1334. #io-channel-cells = <0x01>;
  1335. label = "ina226-dac-avccaux";
  1336. compatible = "ti,ina226";
  1337. reg = <0x4b>;
  1338. phandle = <0x32>;
  1339. shunt-resistor = <0x1388>;
  1340. };
  1341.  
  1342. ina226@42 {
  1343. #io-channel-cells = <0x01>;
  1344. label = "ina226-vcc1v8";
  1345. compatible = "ti,ina226";
  1346. reg = <0x42>;
  1347. phandle = <0x2a>;
  1348. shunt-resistor = <0x7d0>;
  1349. };
  1350.  
  1351. ina226@40 {
  1352. #io-channel-cells = <0x01>;
  1353. label = "ina226-vccint";
  1354. compatible = "ti,ina226";
  1355. reg = <0x40>;
  1356. phandle = <0x28>;
  1357. shunt-resistor = <0x1388>;
  1358. };
  1359.  
  1360. ina226@49 {
  1361. #io-channel-cells = <0x01>;
  1362. label = "ina226-vccint-ams";
  1363. compatible = "ti,ina226";
  1364. reg = <0x49>;
  1365. phandle = <0x30>;
  1366. shunt-resistor = <0x1388>;
  1367. };
  1368. };
  1369.  
  1370. i2c@3 {
  1371. #address-cells = <0x01>;
  1372. #size-cells = <0x00>;
  1373. reg = <0x03>;
  1374. };
  1375.  
  1376. i2c@1 {
  1377. #address-cells = <0x01>;
  1378. #size-cells = <0x00>;
  1379. reg = <0x01>;
  1380. };
  1381.  
  1382. i2c@2 {
  1383. #address-cells = <0x01>;
  1384. #size-cells = <0x00>;
  1385. reg = <0x02>;
  1386.  
  1387. irps5401@45 {
  1388. compatible = "infineon,irps5401";
  1389. reg = <0x45>;
  1390. phandle = <0x6b>;
  1391. };
  1392.  
  1393. irps5401@44 {
  1394. compatible = "infineon,irps5401";
  1395. reg = <0x44>;
  1396. phandle = <0x6a>;
  1397. };
  1398. };
  1399. };
  1400. };
  1401.  
  1402. dma-controller@fd520000 {
  1403. power-domains = <0x11 0x2a>;
  1404. iommus = <0x12 0x14ea>;
  1405. clock-names = "clk_main\0clk_apb";
  1406. interrupts = <0x00 0x7e 0x04>;
  1407. clocks = <0x04 0x13 0x04 0x1f>;
  1408. interrupt-parent = <0x05>;
  1409. xlnx,bus-width = <0x80>;
  1410. compatible = "xlnx,zynqmp-dma-1.0";
  1411. status = "okay";
  1412. reg = <0x00 0xfd520000 0x00 0x1000>;
  1413. phandle = <0x53>;
  1414. #dma-cells = <0x01>;
  1415. };
  1416.  
  1417. display@fd4a0000 {
  1418. power-domains = <0x11 0x29>;
  1419. iommus = <0x12 0xce3>;
  1420. clock-names = "dp_apb_clk\0dp_aud_clk\0dp_vtc_pixel_clk_in";
  1421. reg-names = "dp\0blend\0av_buf";
  1422. assigned-clocks = <0x04 0x12 0x04 0x11 0x04 0x10>;
  1423. u-boot,dm-pre-reloc;
  1424. resets = <0x13 0x03>;
  1425. interrupts = <0x00 0x77 0x04>;
  1426. clocks = <0x24 0x04 0x11 0x04 0x10>;
  1427. interrupt-parent = <0x05>;
  1428. dma-names = "vid0\0vid1\0vid2\0gfx0";
  1429. compatible = "xlnx,zynqmp-dpsub-1.7";
  1430. status = "disabled";
  1431. xlnx,dpaud-reg = <0x22>;
  1432. reg = <0x00 0xfd4a0000 0x00 0x1000 0x00 0xfd4aa000 0x00 0x1000 0x00 0xfd4ab000 0x00 0x1000>;
  1433. phandle = <0x99>;
  1434. dmas = <0x23 0x00 0x23 0x01 0x23 0x02 0x23 0x03>;
  1435.  
  1436. i2c-bus {
  1437. };
  1438.  
  1439. zynqmp_dp_snd_pcm0 {
  1440. dma-names = "tx";
  1441. compatible = "xlnx,dp-snd-pcm0";
  1442. phandle = <0x25>;
  1443. dmas = <0x23 0x04>;
  1444. };
  1445.  
  1446. zynqmp_dp_snd_codec0 {
  1447. clock-names = "aud_clk";
  1448. clocks = <0x04 0x11>;
  1449. compatible = "xlnx,dp-snd-codec";
  1450. phandle = <0x27>;
  1451. };
  1452.  
  1453. zynqmp_dp_snd_card {
  1454. xlnx,dp-snd-pcm = <0x25 0x26>;
  1455. xlnx,dp-snd-codec = <0x27>;
  1456. compatible = "xlnx,dp-snd-card";
  1457. phandle = <0x9a>;
  1458. };
  1459.  
  1460. zynqmp_dp_snd_pcm1 {
  1461. dma-names = "tx";
  1462. compatible = "xlnx,dp-snd-pcm1";
  1463. phandle = <0x26>;
  1464. dmas = <0x23 0x05>;
  1465. };
  1466. };
  1467.  
  1468. dma-controller@ffa90000 {
  1469. power-domains = <0x11 0x2b>;
  1470. clock-names = "clk_main\0clk_apb";
  1471. interrupts = <0x00 0x4e 0x04>;
  1472. clocks = <0x04 0x44 0x04 0x1f>;
  1473. interrupt-parent = <0x05>;
  1474. xlnx,bus-width = <0x40>;
  1475. compatible = "xlnx,zynqmp-dma-1.0";
  1476. status = "okay";
  1477. reg = <0x00 0xffa90000 0x00 0x1000>;
  1478. phandle = <0x5b>;
  1479. #dma-cells = <0x01>;
  1480. };
  1481.  
  1482. dma-controller@fd560000 {
  1483. power-domains = <0x11 0x2a>;
  1484. iommus = <0x12 0x14ee>;
  1485. clock-names = "clk_main\0clk_apb";
  1486. interrupts = <0x00 0x82 0x04>;
  1487. clocks = <0x04 0x13 0x04 0x1f>;
  1488. interrupt-parent = <0x05>;
  1489. xlnx,bus-width = <0x80>;
  1490. compatible = "xlnx,zynqmp-dma-1.0";
  1491. status = "okay";
  1492. reg = <0x00 0xfd560000 0x00 0x1000>;
  1493. phandle = <0x57>;
  1494. #dma-cells = <0x01>;
  1495. };
  1496.  
  1497. smmu@fd800000 {
  1498. #global-interrupts = <0x01>;
  1499. interrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>;
  1500. interrupt-parent = <0x05>;
  1501. #iommu-cells = <0x01>;
  1502. compatible = "arm,mmu-500";
  1503. status = "disabled";
  1504. reg = <0x00 0xfd800000 0x00 0x20000>;
  1505. phandle = <0x12>;
  1506. };
  1507.  
  1508. timer@ff120000 {
  1509. power-domains = <0x11 0x19>;
  1510. timer-width = <0x20>;
  1511. interrupts = <0x00 0x27 0x04 0x00 0x28 0x04 0x00 0x29 0x04>;
  1512. clocks = <0x04 0x1f>;
  1513. interrupt-parent = <0x05>;
  1514. compatible = "cdns,ttc";
  1515. status = "okay";
  1516. reg = <0x00 0xff120000 0x00 0x1000>;
  1517. phandle = <0x8b>;
  1518. };
  1519.  
  1520. watchdog@ff150000 {
  1521. interrupts = <0x00 0x34 0x01>;
  1522. clocks = <0x04 0x70>;
  1523. interrupt-parent = <0x05>;
  1524. timeout-sec = <0x0a>;
  1525. compatible = "cdns,wdt-r1p2";
  1526. status = "okay";
  1527. reg = <0x00 0xff150000 0x00 0x1000>;
  1528. phandle = <0x95>;
  1529. };
  1530.  
  1531. ethernet@ff0c0000 {
  1532. power-domains = <0x11 0x1e>;
  1533. iommus = <0x12 0x875>;
  1534. #address-cells = <0x01>;
  1535. clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
  1536. resets = <0x13 0x1e>;
  1537. interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>;
  1538. clocks = <0x04 0x1f 0x04 0x69 0x04 0x2e 0x04 0x32 0x04 0x2c>;
  1539. #size-cells = <0x00>;
  1540. interrupt-parent = <0x05>;
  1541. compatible = "xlnx,zynqmp-gem\0cdns,gem";
  1542. status = "disabled";
  1543. reg = <0x00 0xff0c0000 0x00 0x1000>;
  1544. phandle = <0x65>;
  1545. reset-names = "gem1_rst";
  1546. };
  1547.  
  1548. can@ff060000 {
  1549. power-domains = <0x11 0x2f>;
  1550. clock-names = "can_clk\0pclk";
  1551. interrupts = <0x00 0x17 0x04>;
  1552. clocks = <0x04 0x3f 0x04 0x1f>;
  1553. interrupt-parent = <0x05>;
  1554. compatible = "xlnx,zynq-can-1.0";
  1555. status = "disabled";
  1556. tx-fifo-depth = <0x40>;
  1557. rx-fifo-depth = <0x40>;
  1558. reg = <0x00 0xff060000 0x00 0x1000>;
  1559. phandle = <0x4e>;
  1560. };
  1561.  
  1562. dma@a1000000 {
  1563. clock-names = "s_axi_lite_aclk\0m_axi_s2mm_aclk";
  1564. interrupts = <0x00 0x5a 0x04>;
  1565. clocks = <0x04 0x47 0x04 0x48>;
  1566. interrupt-parent = <0x05>;
  1567. xlnx,addrwidth = <0x20>;
  1568. compatible = "xlnx,axi-dma-7.1\0xlnx,axi-dma-1.00.a";
  1569. interrupt-names = "s2mm_introut";
  1570. xlnx,sg-length-width = <0x1a>;
  1571. reg = <0x00 0xa1000000 0x00 0x10000>;
  1572. phandle = <0xa8>;
  1573. #dma-cells = <0x01>;
  1574.  
  1575. dma-channel@a1000030 {
  1576. xlnx,device-id = <0x00>;
  1577. interrupts = <0x00 0x5a 0x04>;
  1578. compatible = "xlnx,axi-dma-s2mm-channel";
  1579. dma-channels = <0x01>;
  1580. xlnx,datawidth = <0x40>;
  1581. };
  1582. };
  1583.  
  1584. gpio@a0205000 {
  1585. xlnx,is-dual = <0x00>;
  1586. xlnx,all-inputs-2 = <0x00>;
  1587. clock-names = "s_axi_aclk";
  1588. gpio-controller;
  1589. clocks = <0x04 0x47>;
  1590. xlnx,gpio-width = <0x02>;
  1591. xlnx,all-outputs-2 = <0x00>;
  1592. xlnx,interrupt-present = <0x00>;
  1593. xlnx,dout-default = <0x00>;
  1594. compatible = "xlnx,axi-gpio-2.0\0xlnx,xps-gpio-1.00.a";
  1595. xlnx,all-inputs = <0x00>;
  1596. xlnx,gpio2-width = <0x20>;
  1597. xlnx,tri-default-2 = <0xffffffff>;
  1598. xlnx,dout-default-2 = <0x00>;
  1599. xlnx,all-outputs = <0x01>;
  1600. reg = <0x00 0xa0205000 0x00 0x1000>;
  1601. phandle = <0xa9>;
  1602. #gpio-cells = <0x02>;
  1603. xlnx,tri-default = <0xffffffff>;
  1604. };
  1605.  
  1606. usb@ff9e0000 {
  1607. power-domains = <0x11 0x17>;
  1608. #address-cells = <0x02>;
  1609. clock-names = "bus_clk\0ref_clk";
  1610. assigned-clocks = <0x04 0x21 0x04 0x22>;
  1611. resets = <0x13 0x3c 0x13 0x3e 0x13 0x40>;
  1612. clocks = <0x04 0x21 0x04 0x22>;
  1613. #size-cells = <0x02>;
  1614. compatible = "xlnx,zynqmp-dwc3";
  1615. ranges;
  1616. status = "disabled";
  1617. reg = <0x00 0xff9e0000 0x00 0x100>;
  1618. phandle = <0x92>;
  1619. reset-names = "usb_crst\0usb_hibrst\0usb_apbrst";
  1620.  
  1621. usb@fe300000 {
  1622. iommus = <0x12 0x861>;
  1623. snps,resume-hs-terminations;
  1624. snps,quirk-frame-length-adjustment = <0x20>;
  1625. clock-names = "ref";
  1626. interrupts = <0x00 0x46 0x04 0x00 0x4a 0x04 0x00 0x4c 0x04>;
  1627. clocks = <0x04 0x22>;
  1628. interrupt-parent = <0x05>;
  1629. compatible = "snps,dwc3";
  1630. status = "disabled";
  1631. interrupt-names = "dwc_usb3\0otg\0hiber";
  1632. snps,enable_guctl1_ipd_quirk;
  1633. reg = <0x00 0xfe300000 0x00 0x40000>;
  1634. phandle = <0x93>;
  1635. snps,enable_guctl1_resume_quirk;
  1636. };
  1637. };
  1638.  
  1639. perf-monitor@ffa00000 {
  1640. xlnx,metric-count-width = <0x20>;
  1641. xlnx,have-sampled-metric-cnt = <0x01>;
  1642. xlnx,enable-trace = <0x00>;
  1643. xlnx,global-count-width = <0x20>;
  1644. xlnx,enable-event-count = <0x01>;
  1645. interrupts = <0x00 0x19 0x04>;
  1646. clocks = <0x04 0x1f>;
  1647. xlnx,enable-profile = <0x00>;
  1648. xlnx,metric-count-scale = <0x01>;
  1649. interrupt-parent = <0x05>;
  1650. xlnx,num-monitor-slots = <0x01>;
  1651. compatible = "xlnx,axi-perf-monitor";
  1652. xlnx,num-of-counters = <0x08>;
  1653. reg = <0x00 0xffa00000 0x00 0x10000>;
  1654. phandle = <0x7e>;
  1655. xlnx,metrics-sample-count-width = <0x20>;
  1656. xlnx,enable-event-log = <0x01>;
  1657. };
  1658.  
  1659. dma-controller@ffad0000 {
  1660. power-domains = <0x11 0x2b>;
  1661. clock-names = "clk_main\0clk_apb";
  1662. interrupts = <0x00 0x52 0x04>;
  1663. clocks = <0x04 0x44 0x04 0x1f>;
  1664. interrupt-parent = <0x05>;
  1665. xlnx,bus-width = <0x40>;
  1666. compatible = "xlnx,zynqmp-dma-1.0";
  1667. status = "okay";
  1668. reg = <0x00 0xffad0000 0x00 0x1000>;
  1669. phandle = <0x5f>;
  1670. #dma-cells = <0x01>;
  1671. };
  1672.  
  1673. gpu@fd4b0000 {
  1674. power-domains = <0x11 0x3a>;
  1675. clock-names = "bus\0core";
  1676. interrupts = <0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04>;
  1677. clocks = <0x04 0x18 0x04 0x19>;
  1678. interrupt-parent = <0x05>;
  1679. compatible = "xlnx,zynqmp-mali\0arm,mali-400";
  1680. status = "disabled";
  1681. interrupt-names = "gp\0gpmmu\0pp0\0ppmmu0\0pp1\0ppmmu1";
  1682. reg = <0x00 0xfd4b0000 0x00 0x10000>;
  1683. phandle = <0x59>;
  1684. };
  1685.  
  1686. serial@ff000000 {
  1687. power-domains = <0x11 0x21>;
  1688. clock-names = "uart_clk\0pclk";
  1689. u-boot,dm-pre-reloc;
  1690. cts-override;
  1691. interrupts = <0x00 0x15 0x04>;
  1692. clocks = <0x04 0x38 0x04 0x1f>;
  1693. interrupt-parent = <0x05>;
  1694. device_type = "serial";
  1695. port-number = <0x00>;
  1696. compatible = "xlnx,zynqmp-uart\0cdns,uart-r1p12";
  1697. status = "okay";
  1698. reg = <0x00 0xff000000 0x00 0x1000>;
  1699. phandle = <0x8e>;
  1700. };
  1701.  
  1702. i2c@ff030000 {
  1703. power-domains = <0x11 0x26>;
  1704. pinctrl-names = "default\0gpio";
  1705. #address-cells = <0x01>;
  1706. pinctrl-0 = <0x1a>;
  1707. interrupts = <0x00 0x12 0x04>;
  1708. clocks = <0x04 0x3e>;
  1709. #size-cells = <0x00>;
  1710. interrupt-parent = <0x05>;
  1711. clock-frequency = <0x61a80>;
  1712. compatible = "cdns,i2c-r1p14";
  1713. pinctrl-1 = <0x1b>;
  1714. status = "okay";
  1715. reg = <0x00 0xff030000 0x00 0x1000>;
  1716. phandle = <0x6c>;
  1717. scl-gpios = <0x19 0x10 0x00>;
  1718. sda-gpios = <0x19 0x11 0x00>;
  1719.  
  1720. i2c-mux@74 {
  1721. #address-cells = <0x01>;
  1722. i2c-mux-idle-disconnect;
  1723. #size-cells = <0x00>;
  1724. compatible = "nxp,pca9548";
  1725. reg = <0x74>;
  1726.  
  1727. i2c@0 {
  1728. #address-cells = <0x01>;
  1729. #size-cells = <0x00>;
  1730. reg = <0x00>;
  1731. phandle = <0x6d>;
  1732.  
  1733. eeprom@54 {
  1734. compatible = "atmel,24c128";
  1735. reg = <0x54>;
  1736. phandle = <0x36>;
  1737.  
  1738. mac-address@23 {
  1739. reg = <0x23 0x06>;
  1740. phandle = <0x15>;
  1741. };
  1742. };
  1743. };
  1744.  
  1745. i2c@5 {
  1746. #address-cells = <0x01>;
  1747. #size-cells = <0x00>;
  1748. reg = <0x05>;
  1749. phandle = <0x7a>;
  1750. };
  1751.  
  1752. i2c@3 {
  1753. #address-cells = <0x01>;
  1754. #size-cells = <0x00>;
  1755. reg = <0x03>;
  1756. phandle = <0x76>;
  1757.  
  1758. clock-generator@5d {
  1759. clock-output-names = "si570_mgt";
  1760. factory-fout = <0x9502f90>;
  1761. #clock-cells = <0x00>;
  1762. clock-frequency = <0x8d9ee20>;
  1763. compatible = "silabs,si570";
  1764. reg = <0x5d>;
  1765. phandle = <0x77>;
  1766. temperature-stability = <0x32>;
  1767. };
  1768. };
  1769.  
  1770. i2c@1 {
  1771. #address-cells = <0x01>;
  1772. #size-cells = <0x00>;
  1773. reg = <0x01>;
  1774. phandle = <0x6e>;
  1775.  
  1776. clock-generator@36 {
  1777. #address-cells = <0x01>;
  1778. clock-output-names = "si5341";
  1779. clock-names = "xtal";
  1780. clocks = <0x1c>;
  1781. #size-cells = <0x00>;
  1782. #clock-cells = <0x02>;
  1783. compatible = "silabs,si5341";
  1784. reg = <0x36>;
  1785. phandle = <0x1f>;
  1786.  
  1787. out@6 {
  1788. always-on;
  1789. reg = <0x06>;
  1790. phandle = <0x72>;
  1791. };
  1792.  
  1793. out@2 {
  1794. always-on;
  1795. reg = <0x02>;
  1796. phandle = <0x6f>;
  1797. };
  1798.  
  1799. out@9 {
  1800. always-on;
  1801. reg = <0x09>;
  1802. phandle = <0x73>;
  1803. };
  1804.  
  1805. out@5 {
  1806. always-on;
  1807. reg = <0x05>;
  1808. phandle = <0x71>;
  1809. };
  1810.  
  1811. out@3 {
  1812. always-on;
  1813. reg = <0x03>;
  1814. phandle = <0x70>;
  1815. };
  1816. };
  1817. };
  1818.  
  1819. i2c@6 {
  1820. #address-cells = <0x01>;
  1821. #size-cells = <0x00>;
  1822. reg = <0x06>;
  1823. };
  1824.  
  1825. i2c@4 {
  1826. #address-cells = <0x01>;
  1827. #size-cells = <0x00>;
  1828. reg = <0x04>;
  1829. phandle = <0x78>;
  1830.  
  1831. phc@5b {
  1832. compatible = "idt,8a34001";
  1833. reg = <0x5b>;
  1834. phandle = <0x79>;
  1835. };
  1836. };
  1837.  
  1838. i2c@2 {
  1839. #address-cells = <0x01>;
  1840. #size-cells = <0x00>;
  1841. reg = <0x02>;
  1842. phandle = <0x74>;
  1843.  
  1844. clock-generator@5d {
  1845. clock-output-names = "si570_user_c0";
  1846. factory-fout = <0x11e1a300>;
  1847. #clock-cells = <0x00>;
  1848. clock-frequency = <0x11e1a300>;
  1849. compatible = "silabs,si570";
  1850. reg = <0x5d>;
  1851. phandle = <0x75>;
  1852. temperature-stability = <0x32>;
  1853. };
  1854. };
  1855. };
  1856.  
  1857. i2c-mux@75 {
  1858. #address-cells = <0x01>;
  1859. i2c-mux-idle-disconnect;
  1860. #size-cells = <0x00>;
  1861. compatible = "nxp,pca9548";
  1862. reg = <0x75>;
  1863.  
  1864. i2c@0 {
  1865. #address-cells = <0x01>;
  1866. #size-cells = <0x00>;
  1867. reg = <0x00>;
  1868. };
  1869.  
  1870. i2c@7 {
  1871. #address-cells = <0x01>;
  1872. #size-cells = <0x00>;
  1873. reg = <0x07>;
  1874. };
  1875.  
  1876. i2c@5 {
  1877. #address-cells = <0x01>;
  1878. #size-cells = <0x00>;
  1879. reg = <0x05>;
  1880. };
  1881.  
  1882. i2c@3 {
  1883. #address-cells = <0x01>;
  1884. #size-cells = <0x00>;
  1885. reg = <0x03>;
  1886. };
  1887.  
  1888. i2c@1 {
  1889. #address-cells = <0x01>;
  1890. #size-cells = <0x00>;
  1891. reg = <0x01>;
  1892. phandle = <0x7b>;
  1893.  
  1894. clock-generator@5d {
  1895. clock-output-names = "si570_user_c1";
  1896. factory-fout = <0x11e1a300>;
  1897. #clock-cells = <0x00>;
  1898. clock-frequency = <0x11e1a300>;
  1899. compatible = "silabs,si570";
  1900. reg = <0x5d>;
  1901. phandle = <0x7c>;
  1902. temperature-stability = <0x32>;
  1903. };
  1904. };
  1905.  
  1906. i2c@6 {
  1907. #address-cells = <0x01>;
  1908. #size-cells = <0x00>;
  1909. reg = <0x06>;
  1910. };
  1911.  
  1912. i2c@4 {
  1913. #address-cells = <0x01>;
  1914. #size-cells = <0x00>;
  1915. reg = <0x04>;
  1916. };
  1917.  
  1918. i2c@2 {
  1919. #address-cells = <0x01>;
  1920. #size-cells = <0x00>;
  1921. reg = <0x02>;
  1922. };
  1923. };
  1924. };
  1925.  
  1926. watchdog@fd4d0000 {
  1927. interrupts = <0x00 0x71 0x01>;
  1928. clocks = <0x04 0x4b>;
  1929. interrupt-parent = <0x05>;
  1930. timeout-sec = <0x3c>;
  1931. reset-on-timeout;
  1932. compatible = "cdns,wdt-r1p2";
  1933. status = "okay";
  1934. reg = <0x00 0xfd4d0000 0x00 0x1000>;
  1935. phandle = <0x94>;
  1936. };
  1937.  
  1938. dma-controller@fd530000 {
  1939. power-domains = <0x11 0x2a>;
  1940. iommus = <0x12 0x14eb>;
  1941. clock-names = "clk_main\0clk_apb";
  1942. interrupts = <0x00 0x7f 0x04>;
  1943. clocks = <0x04 0x13 0x04 0x1f>;
  1944. interrupt-parent = <0x05>;
  1945. xlnx,bus-width = <0x80>;
  1946. compatible = "xlnx,zynqmp-dma-1.0";
  1947. status = "okay";
  1948. reg = <0x00 0xfd530000 0x00 0x1000>;
  1949. phandle = <0x54>;
  1950. #dma-cells = <0x01>;
  1951. };
  1952.  
  1953. phy@fd400000 {
  1954. clock-names = "ref2\0ref3";
  1955. reg-names = "serdes\0siou";
  1956. clocks = <0x1f 0x00 0x02 0x1f 0x00 0x03>;
  1957. #phy-cells = <0x04>;
  1958. compatible = "xlnx,zynqmp-psgtr-v1.1";
  1959. status = "okay";
  1960. reg = <0x00 0xfd400000 0x00 0x40000 0x00 0xfd3d0000 0x00 0x1000>;
  1961. phandle = <0x20>;
  1962. };
  1963.  
  1964. dma-controller@fd570000 {
  1965. power-domains = <0x11 0x2a>;
  1966. iommus = <0x12 0x14ef>;
  1967. clock-names = "clk_main\0clk_apb";
  1968. interrupts = <0x00 0x83 0x04>;
  1969. clocks = <0x04 0x13 0x04 0x1f>;
  1970. interrupt-parent = <0x05>;
  1971. xlnx,bus-width = <0x80>;
  1972. compatible = "xlnx,zynqmp-dma-1.0";
  1973. status = "okay";
  1974. reg = <0x00 0xfd570000 0x00 0x1000>;
  1975. phandle = <0x58>;
  1976. #dma-cells = <0x01>;
  1977. };
  1978.  
  1979. clocking1 {
  1980. clock-output-names = "fabric_clk";
  1981. assigned-clocks = <0x04 0x48>;
  1982. assigned-clock-rates = <0x11e19751>;
  1983. clocks = <0x04 0x48>;
  1984. #clock-cells = <0x00>;
  1985. compatible = "xlnx,fclk";
  1986. phandle = <0xa7>;
  1987. };
  1988.  
  1989. spi@ff0f0000 {
  1990. power-domains = <0x11 0x2d>;
  1991. iommus = <0x12 0x873>;
  1992. #address-cells = <0x01>;
  1993. num-cs = <0x02>;
  1994. clock-names = "ref_clk\0pclk";
  1995. spi-tx-bus-width = <0x04>;
  1996. u-boot,dm-pre-reloc;
  1997. is-dual = <0x01>;
  1998. interrupts = <0x00 0x0f 0x04>;
  1999. clocks = <0x04 0x35 0x04 0x1f>;
  2000. #size-cells = <0x00>;
  2001. spi-rx-bus-width = <0x04>;
  2002. interrupt-parent = <0x05>;
  2003. compatible = "xlnx,zynqmp-qspi-1.0";
  2004. status = "okay";
  2005. reg = <0x00 0xff0f0000 0x00 0x1000 0x00 0xc0000000 0x00 0x8000000>;
  2006. phandle = <0x82>;
  2007.  
  2008. flash@0 {
  2009. #address-cells = <0x01>;
  2010. spi-tx-bus-width = <0x04>;
  2011. #size-cells = <0x01>;
  2012. spi-max-frequency = <0x66ff300>;
  2013. spi-rx-bus-width = <0x04>;
  2014. compatible = "m25p80\0jedec,spi-nor";
  2015. reg = <0x00 0x01>;
  2016. phandle = <0x83>;
  2017. parallel-memories = <0x00 0x10000000 0x00 0x10000000>;
  2018.  
  2019. partition@2 {
  2020. label = "qspi-kernel";
  2021. reg = <0x4040000 0x2400000>;
  2022. };
  2023.  
  2024. partition@0 {
  2025. label = "qspi-boot";
  2026. reg = <0x00 0x4000000>;
  2027. };
  2028.  
  2029. partition@1 {
  2030. label = "qspi-bootenv";
  2031. reg = <0x4000000 0x40000>;
  2032. };
  2033. };
  2034. };
  2035.  
  2036. timer@ff130000 {
  2037. power-domains = <0x11 0x1a>;
  2038. timer-width = <0x20>;
  2039. interrupts = <0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04>;
  2040. clocks = <0x04 0x1f>;
  2041. interrupt-parent = <0x05>;
  2042. compatible = "cdns,ttc";
  2043. status = "okay";
  2044. reg = <0x00 0xff130000 0x00 0x1000>;
  2045. phandle = <0x8c>;
  2046. };
  2047.  
  2048. spi@ff040000 {
  2049. power-domains = <0x11 0x23>;
  2050. #address-cells = <0x01>;
  2051. clock-names = "ref_clk\0pclk";
  2052. interrupts = <0x00 0x13 0x04>;
  2053. clocks = <0x04 0x3a 0x04 0x1f>;
  2054. #size-cells = <0x00>;
  2055. interrupt-parent = <0x05>;
  2056. compatible = "cdns,spi-r1p6";
  2057. status = "disabled";
  2058. reg = <0x00 0xff040000 0x00 0x1000>;
  2059. phandle = <0x88>;
  2060. };
  2061.  
  2062. ethernet@ff0d0000 {
  2063. power-domains = <0x11 0x1f>;
  2064. iommus = <0x12 0x876>;
  2065. #address-cells = <0x01>;
  2066. clock-names = "pclk\0hclk\0tx_clk\0rx_clk\0tsu_clk";
  2067. resets = <0x13 0x1f>;
  2068. interrupts = <0x00 0x3d 0x04 0x00 0x3d 0x04>;
  2069. clocks = <0x04 0x1f 0x04 0x6a 0x04 0x2f 0x04 0x33 0x04 0x2c>;
  2070. #size-cells = <0x00>;
  2071. interrupt-parent = <0x05>;
  2072. compatible = "xlnx,zynqmp-gem\0cdns,gem";
  2073. status = "disabled";
  2074. reg = <0x00 0xff0d0000 0x00 0x1000>;
  2075. phandle = <0x66>;
  2076. reset-names = "gem2_rst";
  2077. };
  2078.  
  2079. afi0 {
  2080. config-afi = <0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x00 0x04 0x00 0x05 0x00 0x06 0x00 0x07 0x00 0x08 0x00 0x09 0x00 0x0a 0x00 0x0b 0x00 0x0c 0x00 0x0d 0x00 0x0e 0xa00 0x0f 0x00>;
  2081. compatible = "xlnx,afi-fpga";
  2082. phandle = <0xa5>;
  2083. };
  2084.  
  2085. can@ff070000 {
  2086. power-domains = <0x11 0x30>;
  2087. clock-names = "can_clk\0pclk";
  2088. interrupts = <0x00 0x18 0x04>;
  2089. clocks = <0x04 0x40 0x04 0x1f>;
  2090. interrupt-parent = <0x05>;
  2091. compatible = "xlnx,zynq-can-1.0";
  2092. status = "disabled";
  2093. tx-fifo-depth = <0x40>;
  2094. rx-fifo-depth = <0x40>;
  2095. reg = <0x00 0xff070000 0x00 0x1000>;
  2096. phandle = <0x4f>;
  2097. };
  2098.  
  2099. dma-controller@ffaa0000 {
  2100. power-domains = <0x11 0x2b>;
  2101. clock-names = "clk_main\0clk_apb";
  2102. interrupts = <0x00 0x4f 0x04>;
  2103. clocks = <0x04 0x44 0x04 0x1f>;
  2104. interrupt-parent = <0x05>;
  2105. xlnx,bus-width = <0x40>;
  2106. compatible = "xlnx,zynqmp-dma-1.0";
  2107. status = "okay";
  2108. reg = <0x00 0xffaa0000 0x00 0x1000>;
  2109. phandle = <0x5c>;
  2110. #dma-cells = <0x01>;
  2111. };
  2112.  
  2113. perf-monitor@ffa10000 {
  2114. xlnx,metric-count-width = <0x20>;
  2115. xlnx,have-sampled-metric-cnt = <0x01>;
  2116. xlnx,enable-trace = <0x00>;
  2117. xlnx,global-count-width = <0x20>;
  2118. xlnx,enable-event-count = <0x01>;
  2119. interrupts = <0x00 0x19 0x04>;
  2120. clocks = <0x04 0x1f>;
  2121. xlnx,enable-profile = <0x00>;
  2122. xlnx,metric-count-scale = <0x01>;
  2123. interrupt-parent = <0x05>;
  2124. xlnx,num-monitor-slots = <0x01>;
  2125. compatible = "xlnx,axi-perf-monitor";
  2126. xlnx,num-of-counters = <0x08>;
  2127. reg = <0x00 0xffa10000 0x00 0x10000>;
  2128. phandle = <0x81>;
  2129. xlnx,metrics-sample-count-width = <0x20>;
  2130. xlnx,enable-event-log = <0x01>;
  2131. };
  2132.  
  2133. mmc@ff160000 {
  2134. power-domains = <0x11 0x27>;
  2135. iommus = <0x12 0x870>;
  2136. clock-output-names = "clk_out_sd0\0clk_in_sd0";
  2137. clock-names = "clk_xin\0clk_ahb";
  2138. assigned-clocks = <0x04 0x36>;
  2139. u-boot,dm-pre-reloc;
  2140. resets = <0x13 0x26>;
  2141. interrupts = <0x00 0x30 0x04>;
  2142. clocks = <0x04 0x36 0x04 0x1f>;
  2143. #clock-cells = <0x01>;
  2144. interrupt-parent = <0x05>;
  2145. compatible = "xlnx,zynqmp-8.9a\0arasan,sdhci-8.9a";
  2146. status = "disabled";
  2147. reg = <0x00 0xff160000 0x00 0x1000>;
  2148. phandle = <0x86>;
  2149. };
  2150.  
  2151. dma-controller@ffae0000 {
  2152. power-domains = <0x11 0x2b>;
  2153. clock-names = "clk_main\0clk_apb";
  2154. interrupts = <0x00 0x53 0x04>;
  2155. clocks = <0x04 0x44 0x04 0x1f>;
  2156. interrupt-parent = <0x05>;
  2157. xlnx,bus-width = <0x40>;
  2158. compatible = "xlnx,zynqmp-dma-1.0";
  2159. status = "okay";
  2160. reg = <0x00 0xffae0000 0x00 0x1000>;
  2161. phandle = <0x60>;
  2162. };
  2163.  
  2164. perf-monitor@fd490000 {
  2165. xlnx,metric-count-width = <0x20>;
  2166. xlnx,have-sampled-metric-cnt = <0x01>;
  2167. xlnx,enable-trace = <0x00>;
  2168. xlnx,global-count-width = <0x20>;
  2169. xlnx,enable-event-count = <0x01>;
  2170. interrupts = <0x00 0x7b 0x04>;
  2171. clocks = <0x04 0x1c>;
  2172. xlnx,enable-profile = <0x00>;
  2173. xlnx,metric-count-scale = <0x01>;
  2174. interrupt-parent = <0x05>;
  2175. xlnx,num-monitor-slots = <0x01>;
  2176. compatible = "xlnx,axi-perf-monitor";
  2177. xlnx,num-of-counters = <0x08>;
  2178. reg = <0x00 0xfd490000 0x00 0x10000>;
  2179. phandle = <0x80>;
  2180. xlnx,metrics-sample-count-width = <0x20>;
  2181. xlnx,enable-event-log = <0x00>;
  2182. };
  2183.  
  2184. serial@ff010000 {
  2185. power-domains = <0x11 0x22>;
  2186. clock-names = "uart_clk\0pclk";
  2187. u-boot,dm-pre-reloc;
  2188. interrupts = <0x00 0x16 0x04>;
  2189. clocks = <0x04 0x39 0x04 0x1f>;
  2190. interrupt-parent = <0x05>;
  2191. compatible = "xlnx,zynqmp-uart\0cdns,uart-r1p12";
  2192. status = "disabled";
  2193. reg = <0x00 0xff010000 0x00 0x1000>;
  2194. phandle = <0x8f>;
  2195. };
  2196.  
  2197. dma-controller@fd500000 {
  2198. power-domains = <0x11 0x2a>;
  2199. iommus = <0x12 0x14e8>;
  2200. clock-names = "clk_main\0clk_apb";
  2201. interrupts = <0x00 0x7c 0x04>;
  2202. clocks = <0x04 0x13 0x04 0x1f>;
  2203. interrupt-parent = <0x05>;
  2204. xlnx,bus-width = <0x80>;
  2205. compatible = "xlnx,zynqmp-dma-1.0";
  2206. status = "okay";
  2207. reg = <0x00 0xfd500000 0x00 0x1000>;
  2208. phandle = <0x51>;
  2209. #dma-cells = <0x01>;
  2210. };
  2211.  
  2212. ahci@fd0c0000 {
  2213. power-domains = <0x11 0x1c>;
  2214. ceva,p0-comwake-params = <0x614080e>;
  2215. phy-names = "sata-phy";
  2216. ceva,p0-retry-params = <0x96a43ffc>;
  2217. ceva,p0-burst-params = <0x13084a06>;
  2218. resets = <0x13 0x10>;
  2219. interrupts = <0x00 0x85 0x04>;
  2220. clocks = <0x04 0x16>;
  2221. interrupt-parent = <0x05>;
  2222. xlnx,tz-nonsecure-sata0 = <0x00>;
  2223. ceva,p1-retry-params = <0x96a43ffc>;
  2224. ceva,p1-burst-params = <0x13084a06>;
  2225. ceva,p1-cominit-params = <0x18401828>;
  2226. compatible = "ceva,ahci-1v84";
  2227. status = "okay";
  2228. phys = <0x20 0x03 0x01 0x01 0x03>;
  2229. reg = <0x00 0xfd0c0000 0x00 0x2000>;
  2230. phandle = <0x85>;
  2231. ceva,p0-cominit-params = <0x18401828>;
  2232. xlnx,tz-nonsecure-sata1 = <0x00>;
  2233. ceva,p1-comwake-params = <0x614080e>;
  2234. };
  2235.  
  2236. cci@fd6e0000 {
  2237. #address-cells = <0x01>;
  2238. #size-cells = <0x01>;
  2239. compatible = "arm,cci-400";
  2240. ranges = <0x00 0x00 0xfd6e0000 0x10000>;
  2241. status = "okay";
  2242. reg = <0x00 0xfd6e0000 0x00 0x9000>;
  2243. phandle = <0x50>;
  2244.  
  2245. pmu@9000 {
  2246. interrupts = <0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04>;
  2247. interrupt-parent = <0x05>;
  2248. compatible = "arm,cci-400-pmu,r1";
  2249. reg = <0x9000 0x5000>;
  2250. };
  2251. };
  2252.  
  2253. dma-controller@fd540000 {
  2254. power-domains = <0x11 0x2a>;
  2255. iommus = <0x12 0x14ec>;
  2256. clock-names = "clk_main\0clk_apb";
  2257. interrupts = <0x00 0x80 0x04>;
  2258. clocks = <0x04 0x13 0x04 0x1f>;
  2259. interrupt-parent = <0x05>;
  2260. xlnx,bus-width = <0x80>;
  2261. compatible = "xlnx,zynqmp-dma-1.0";
  2262. status = "okay";
  2263. reg = <0x00 0xfd540000 0x00 0x1000>;
  2264. phandle = <0x55>;
  2265. #dma-cells = <0x01>;
  2266. };
  2267.  
  2268. pcie@fd0e0000 {
  2269. power-domains = <0x11 0x3b>;
  2270. iommus = <0x12 0x4d0>;
  2271. #address-cells = <0x03>;
  2272. bus-range = <0x00 0xff>;
  2273. reg-names = "breg\0pcireg\0cfg";
  2274. interrupts = <0x00 0x76 0x04 0x00 0x75 0x04 0x00 0x74 0x04 0x00 0x73 0x04 0x00 0x72 0x04>;
  2275. clocks = <0x04 0x17>;
  2276. interrupt-map = <0x00 0x00 0x00 0x01 0x1e 0x01 0x00 0x00 0x00 0x02 0x1e 0x02 0x00 0x00 0x00 0x03 0x1e 0x03 0x00 0x00 0x00 0x04 0x1e 0x04>;
  2277. #size-cells = <0x02>;
  2278. interrupt-parent = <0x05>;
  2279. msi-controller;
  2280. device_type = "pci";
  2281. interrupt-map-mask = <0x00 0x00 0x00 0x07>;
  2282. compatible = "xlnx,nwl-pcie-2.11";
  2283. ranges = <0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00>;
  2284. #interrupt-cells = <0x01>;
  2285. status = "disabled";
  2286. interrupt-names = "misc\0dummy\0intx\0msi1\0msi0";
  2287. reg = <0x00 0xfd0e0000 0x00 0x1000 0x00 0xfd480000 0x00 0x1000 0x80 0x00 0x00 0x1000000>;
  2288. phandle = <0x1d>;
  2289. msi-parent = <0x1d>;
  2290.  
  2291. legacy-interrupt-controller {
  2292. #address-cells = <0x00>;
  2293. #interrupt-cells = <0x01>;
  2294. phandle = <0x1e>;
  2295. interrupt-controller;
  2296. };
  2297. };
  2298. };
  2299.  
  2300. ina226-vcc1v8 {
  2301. io-channels = <0x2a 0x00 0x2a 0x01 0x2a 0x02 0x2a 0x03>;
  2302. compatible = "iio-hwmon";
  2303. };
  2304. };
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