`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    07:04:55 01/14/2020
// Design Name:
// Module Name:    swcounterupdated
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module swcounterupdated(
	//inputs
	CLK, RST,
	//outputs
	M_H, M_L, S_H, S_L, PSE
    );

	output reg[3:0] M_H = 4'b0; //tens digit of minutes
   output reg[3:0] M_L = 4'b0; //ones digit of minutes
	output reg[3:0] S_H = 4'b0; //tens digit of seconds
   output reg[3:0] S_L = 4'b0; //ones digit of seconds
	output reg[0:0] PSE = 1'b0;

   input RST; //reset button
   input CLK; //2 Hz clock

	always @(posedge CLK)
	begin
		if(RST)
		begin
			M_H = 4'b0; //tens digit of minutes
			M_L = 4'b0; //ones digit of minutes
			S_H = 4'b0; //tens digit of seconds
			S_L = 4'b0; //ones digit of seconds
		end

		if(S_L == 4'b1010)
		begin
			S_H = S_H + 1;
			S_L = 4'b0;
		end
		else
			S_L = S_L + 1;
		begin
		end

		if(S_H == 4'b0110)
		begin
			M_L = M_L + 1;
			S_H = 4'b0;
		end
		else
			//S_H = S_H + 1;
		begin
		end

		if(M_L == 4'b1010)
		begin
			M_H = M_H + 1;
			M_L = 4'b0;
		end
		else
			//M_L = M_L + 1;
		begin
		end

		if(M_H == 4'b0110)
		begin
			PSE = 1;
		end
		else
			//M_H = M_H + 1;
		begin
		end

	end


endmodule