library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adc_dac_interface is port
(
CLK_SAMP : in std_logic;
reset : in std_logic;
enable_in : in std_logic;
Real_in_from_ADC : in std_logic_vector(11 downto 0);--receiver side i/p
imag_in_from_ADC : in std_logic_vector(11 downto 0); --receiver side i/p

Real_adc_to_phy : out std_logic_vector(15 downto 0);--receiver side 0/p
imag_adc_to_phy : out std_logic_vector(15 downto 0);--receiver side o/p

ADC_CLK1 : out std_logic;
ADC_CLK2 : out std_logic;
enable_out:out std_logic
);
end entity;

architecture beh of adc_dac_interface is

begin

process(CLK_SAMP,reset)
begin
if reset='1' then
enable_out<='0';
real_adc_to_phy<=(others=>'0');
imag_adc_to_phy<=(others=>'0');

elsif CLK_SAMP='1' and CLK_SAMP'event then

real_adc_to_phy<=Real_in_from_ADC (11)&Real_in_from_ADC (11)&Real_in_from_ADC (11)&Real_in_from_ADC (11)&Real_in_from_ADC ;
imag_adc_to_phy<= imag_in_from_ADC(11)& imag_in_from_ADC(11)& imag_in_from_ADC(11)& imag_in_from_ADC(11)& imag_in_from_ADC;
enable_out<=enable_in;

end if;

end process;

ADC_CLK1<=CLK_SAMP;
ADC_CLK2<=CLK_SAMP;

end beh;