Lab 6

module main(clk, out
    );

     input clk;
     output out;
     wire clk;
     reg[7:0] out;

     reg[31:0] instru_mem[7:0], register[7:0];
     reg[31:0] instruction;
     reg[2:0] PC;

    initial begin
        out = 0;
        PC = 0;
        register[0] = 0;
        register[1] = 0;
        register[2] = 0;
        register[3] = 0;
        register[4] = 0;
        register[5] = 3;
        register[6] = 6;
        register[7] = 0;

        instru_mem[0] = 32'b00000000110001010011100000000010;
        instru_mem[1] = 32'b00000000110001010011100000000100;
        instru_mem[2] = 32'b00000000110001010011100000000000;
        instru_mem[3] = 32'b00000000110001010011100000000001;
        instru_mem[4] = 0;
        instru_mem[5] = 0;
        instru_mem[6] = 0;
        instru_mem[7] = 0;
    end

    always@(posedge clk) begin
        instruction = instru_mem[PC];
        PC = PC+1;
    end

    always@(PC) begin
        if(instruction[5:0] == 0) begin
            register[instruction[15:11]] <= register[instruction[25:21]] & register[instruction[20:16]];
        end else
        if(instruction[5:0] == 1) begin
            register[instruction[15:11]] <= register[instruction[25:21]] | register[instruction[20:16]];
        end else
        if(instruction[5:0] == 2) begin
            register[instruction[15:11]] <= register[instruction[25:21]] + register[instruction[20:16]];
        end else
        if(instruction[5:0] == 4) begin
            register[instruction[15:11]] <= register[instruction[25:21]] - register[instruction[20:16]];
        end

        out = register[7][7:0];

    end


endmodule