module D_latch (D, Clk, Q);
input D, Clk;
output reg Q;
always @ (D, Clk)
if (Clk)
Q = D;
endmodule


module FDD_negedge(clk,D,Q);

input clk,D;
output reg Q;

always @(negedge clk)


Q = D;

endmodule


module FDD_posedge(clk,D,Q);

input clk,D;
output reg Q;

always @(posedge clk)


Q = D;

endmodule

module latch_FDDP_FDDN(clk,D,Qa,Qb,Qc);

input clk,D;
output Qa,Qb,Qc;

D_latch d1(D,clk,Qa);
FDD_posedge d2(clk,D,Qb);
FDD_negedge d3(clk,D,Qc);

endmodule