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  1. Path #1: Setup slack is -0.364 (VIOLATED)
  2. ===================================================================
  3. From Node : LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[1]
  4. To Node : LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[1]
  5. Launch Clock : LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  6. Latch Clock : LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  7.  
  8. Data Arrival Path:
  9.  
  10. Total (ns) Incr (ns) Type Element
  11. ========== ========= == ==== ===================================
  12. 0.962 0.962 launch edge time
  13. 0.962 0.000 source latency
  14. 0.962 0.000 lvds_imx6_clk_p
  15. 0.962 0.000 RR IC lvds_imx6_clk_p~input|i
  16. 1.862 0.900 RR CELL lvds_imx6_clk_p~input|o
  17. 2.137 0.275 RR IC LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|inclk
  18. 2.447 0.310 RR CELL LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|outclk
  19. 3.689 1.242 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|coreclkin
  20. 4.018 0.329 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|clkout
  21. 4.018 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin
  22. 4.203 0.185 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
  23. 4.203 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]
  24. 5.950 1.747 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  25. 6.426 0.476 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|inclk
  26. 6.744 0.318 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|outclk
  27. 9.052 2.308 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:ALTDDIO_IN_component|auto_generated|ddio_ina[1]|clk
  28. 9.783 0.731 RR CELL LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[1]
  29. 9.783 0.000 uTco LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[1]
  30. 9.882 0.099 FF CELL LvdsReceiver_inst0|\SDR_ShiftRegister:ALTDDIO_IN_component|auto_generated|ddio_ina[1]|regouthi
  31. 10.790 0.908 FF IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[1]|asdata
  32. 11.402 0.612 FF CELL LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[1]
  33.  
  34. Data Required Path:
  35.  
  36. Total (ns) Incr (ns) Type Element
  37. ========== ========= == ==== ===================================
  38. 2.886 2.886 latch edge time
  39. 2.886 0.000 source latency
  40. 2.886 0.000 lvds_imx6_clk_p
  41. 2.886 0.000 RR IC lvds_imx6_clk_p~input|i
  42. 3.786 0.900 RR CELL lvds_imx6_clk_p~input|o
  43. 3.858 0.072 RR IC LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|inclk
  44. 4.143 0.285 RR CELL LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|outclk
  45. 5.327 1.184 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|coreclkin
  46. 5.632 0.305 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|clkout
  47. 5.632 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin
  48. 5.481 -0.151 RR COMP LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
  49. 5.481 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]
  50. 6.949 1.468 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  51. 7.354 0.405 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|inclk
  52. 7.646 0.292 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|outclk
  53. 9.551 1.905 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[1]|clk
  54. 10.045 0.494 RR CELL LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[1]
  55. 11.108 1.063 clock pessimism removed
  56. 11.038 -0.070 clock uncertainty
  57. 11.038 0.000 uTsu LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[1]
  58.  
  59. Data Arrival Time : 11.402
  60. Data Required Time : 11.038
  61. Slack : -0.364 (VIOLATED)
  62. ===================================================================
  63.  
  64. Path #2: Setup slack is -0.283 (VIOLATED)
  65. ===================================================================
  66. From Node : LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[0]
  67. To Node : LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[0]
  68. Launch Clock : LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  69. Latch Clock : LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  70.  
  71. Data Arrival Path:
  72.  
  73. Total (ns) Incr (ns) Type Element
  74. ========== ========= == ==== ===================================
  75. 0.962 0.962 launch edge time
  76. 0.962 0.000 source latency
  77. 0.962 0.000 lvds_imx6_clk_p
  78. 0.962 0.000 RR IC lvds_imx6_clk_p~input|i
  79. 1.862 0.900 RR CELL lvds_imx6_clk_p~input|o
  80. 2.137 0.275 RR IC LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|inclk
  81. 2.447 0.310 RR CELL LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|outclk
  82. 3.689 1.242 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|coreclkin
  83. 4.018 0.329 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|clkout
  84. 4.018 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin
  85. 4.203 0.185 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
  86. 4.203 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]
  87. 5.950 1.747 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  88. 6.426 0.476 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|inclk
  89. 6.744 0.318 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|outclk
  90. 9.066 2.322 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:ALTDDIO_IN_component|auto_generated|ddio_ina[0]|clk
  91. 9.797 0.731 RR CELL LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[0]
  92. 9.797 0.000 uTco LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[0]
  93. 9.896 0.099 FF CELL LvdsReceiver_inst0|\SDR_ShiftRegister:ALTDDIO_IN_component|auto_generated|ddio_ina[0]|regouthi
  94. 10.753 0.857 FF IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[0]|asdata
  95. 11.365 0.612 FF CELL LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[0]
  96.  
  97. Data Required Path:
  98.  
  99. Total (ns) Incr (ns) Type Element
  100. ========== ========= == ==== ===================================
  101. 2.886 2.886 latch edge time
  102. 2.886 0.000 source latency
  103. 2.886 0.000 lvds_imx6_clk_p
  104. 2.886 0.000 RR IC lvds_imx6_clk_p~input|i
  105. 3.786 0.900 RR CELL lvds_imx6_clk_p~input|o
  106. 3.858 0.072 RR IC LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|inclk
  107. 4.143 0.285 RR CELL LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|outclk
  108. 5.327 1.184 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|coreclkin
  109. 5.632 0.305 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|clkout
  110. 5.632 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin
  111. 5.481 -0.151 RR COMP LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
  112. 5.481 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]
  113. 6.949 1.468 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  114. 7.354 0.405 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|inclk
  115. 7.646 0.292 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|outclk
  116. 9.577 1.931 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[0]|clk
  117. 10.071 0.494 RR CELL LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[0]
  118. 11.152 1.081 clock pessimism removed
  119. 11.082 -0.070 clock uncertainty
  120. 11.082 0.000 uTsu LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[0]
  121.  
  122. Data Arrival Time : 11.365
  123. Data Required Time : 11.082
  124. Slack : -0.283 (VIOLATED)
  125. ===================================================================
  126.  
  127. Path #3: Setup slack is -0.034 (VIOLATED)
  128. ===================================================================
  129. From Node : LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[2]
  130. To Node : LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[2]
  131. Launch Clock : LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  132. Latch Clock : LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  133.  
  134. Data Arrival Path:
  135.  
  136. Total (ns) Incr (ns) Type Element
  137. ========== ========= == ==== ===================================
  138. 0.962 0.962 launch edge time
  139. 0.962 0.000 source latency
  140. 0.962 0.000 lvds_imx6_clk_p
  141. 0.962 0.000 RR IC lvds_imx6_clk_p~input|i
  142. 1.862 0.900 RR CELL lvds_imx6_clk_p~input|o
  143. 2.137 0.275 RR IC LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|inclk
  144. 2.447 0.310 RR CELL LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|outclk
  145. 3.689 1.242 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|coreclkin
  146. 4.018 0.329 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|clkout
  147. 4.018 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin
  148. 4.203 0.185 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
  149. 4.203 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]
  150. 5.950 1.747 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  151. 6.426 0.476 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|inclk
  152. 6.744 0.318 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|outclk
  153. 9.063 2.319 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:ALTDDIO_IN_component|auto_generated|ddio_ina[2]|clk
  154. 9.794 0.731 RR CELL LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[2]
  155. 9.794 0.000 uTco LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[2]
  156. 9.893 0.099 FF CELL LvdsReceiver_inst0|\SDR_ShiftRegister:ALTDDIO_IN_component|auto_generated|ddio_ina[2]|regouthi
  157. 10.778 0.885 FF IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[2]~feeder|dataf
  158. 10.855 0.077 FF CELL LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[2]~feeder|combout
  159. 10.855 0.000 FF IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[2]|d
  160. 11.115 0.260 FF CELL LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[2]
  161.  
  162. Data Required Path:
  163.  
  164. Total (ns) Incr (ns) Type Element
  165. ========== ========= == ==== ===================================
  166. 2.886 2.886 latch edge time
  167. 2.886 0.000 source latency
  168. 2.886 0.000 lvds_imx6_clk_p
  169. 2.886 0.000 RR IC lvds_imx6_clk_p~input|i
  170. 3.786 0.900 RR CELL lvds_imx6_clk_p~input|o
  171. 3.858 0.072 RR IC LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|inclk
  172. 4.143 0.285 RR CELL LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|outclk
  173. 5.327 1.184 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|coreclkin
  174. 5.632 0.305 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|clkout
  175. 5.632 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin
  176. 5.481 -0.151 RR COMP LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
  177. 5.481 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]
  178. 6.949 1.468 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  179. 7.354 0.405 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|inclk
  180. 7.646 0.292 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|outclk
  181. 9.573 1.927 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[2]|clk
  182. 10.070 0.497 RR CELL LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[2]
  183. 11.151 1.081 clock pessimism removed
  184. 11.081 -0.070 clock uncertainty
  185. 11.081 0.000 uTsu LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[2]
  186.  
  187. Data Arrival Time : 11.115
  188. Data Required Time : 11.081
  189. Slack : -0.034 (VIOLATED)
  190. ===================================================================
  191.  
  192. Path #4: Setup slack is 0.077
  193. ===================================================================
  194. From Node : LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[3]
  195. To Node : LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[3]
  196. Launch Clock : LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  197. Latch Clock : LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  198.  
  199. Data Arrival Path:
  200.  
  201. Total (ns) Incr (ns) Type Element
  202. ========== ========= == ==== ===================================
  203. 0.962 0.962 launch edge time
  204. 0.962 0.000 source latency
  205. 0.962 0.000 lvds_imx6_clk_p
  206. 0.962 0.000 RR IC lvds_imx6_clk_p~input|i
  207. 1.862 0.900 RR CELL lvds_imx6_clk_p~input|o
  208. 2.137 0.275 RR IC LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|inclk
  209. 2.447 0.310 RR CELL LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|outclk
  210. 3.689 1.242 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|coreclkin
  211. 4.018 0.329 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|clkout
  212. 4.018 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin
  213. 4.203 0.185 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
  214. 4.203 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]
  215. 5.950 1.747 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  216. 6.426 0.476 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|inclk
  217. 6.744 0.318 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|outclk
  218. 9.073 2.329 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:ALTDDIO_IN_component|auto_generated|ddio_ina[3]|clk
  219. 9.804 0.731 RR CELL LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[3]
  220. 9.804 0.000 uTco LvdsReceiver:LvdsReceiver_inst0|altddio_in:\SDR_ShiftRegister:ALTDDIO_IN_component|ddio_in_p6h:auto_generated|dataout_h[3]
  221. 9.920 0.116 RR CELL LvdsReceiver_inst0|\SDR_ShiftRegister:ALTDDIO_IN_component|auto_generated|ddio_ina[3]|regouthi
  222. 10.662 0.742 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[3]~feeder|dataf
  223. 10.745 0.083 RR CELL LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[3]~feeder|combout
  224. 10.745 0.000 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[3]|d
  225. 11.007 0.262 RR CELL LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[3]
  226.  
  227. Data Required Path:
  228.  
  229. Total (ns) Incr (ns) Type Element
  230. ========== ========= == ==== ===================================
  231. 2.886 2.886 latch edge time
  232. 2.886 0.000 source latency
  233. 2.886 0.000 lvds_imx6_clk_p
  234. 2.886 0.000 RR IC lvds_imx6_clk_p~input|i
  235. 3.786 0.900 RR CELL lvds_imx6_clk_p~input|o
  236. 3.858 0.072 RR IC LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|inclk
  237. 4.143 0.285 RR CELL LvdsReceiver_inst0|\CycloneV_Family:LvdsClkCtrl|auto_generated|sd1|outclk
  238. 5.327 1.184 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|coreclkin
  239. 5.632 0.305 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT|clkout
  240. 5.632 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin
  241. 5.481 -0.151 RR COMP LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]
  242. 5.481 0.000 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]
  243. 6.949 1.468 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk
  244. 7.354 0.405 RR IC LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|inclk
  245. 7.646 0.292 RR CELL LvdsReceiver_inst0|\CycloneV_Family:SDR_Pll:serial_input_pll|lvdsinputsdrpll_inst|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0|outclk
  246. 9.587 1.941 RR IC LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[3]|clk
  247. 10.073 0.486 RR CELL LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[3]
  248. 11.154 1.081 clock pessimism removed
  249. 11.084 -0.070 clock uncertainty
  250. 11.084 0.000 uTsu LvdsReceiver:LvdsReceiver_inst0|\SDR_ShiftRegister:Signal_Data_Q[3]
  251.  
  252. Data Arrival Time : 11.007
  253. Data Required Time : 11.084
  254. Slack : 0.077
  255. ===================================================================
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