library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity m9_adder is

generic (width : positive := 5);
port (
		cin    : in  std_logic;
		a, b   : in  std_logic_vector (width - 1 downto 0);
		sum_ergebnis    : inout std_logic_vector (width - 1 downto 0);
		cout   : inout std_logic);

end m9_adder;

architecture Behavioral of m9_adder is

component m9_fulladd
		port (a, b, cin  : in  std_logic;
		sum , cout : out std_logic);

end component;



signal s_null, s_eins, cnext  : std_logic_vector (width -1 downto 0);
signal cout_null, cout_eins  : std_logic_vector (width -1 downto 0);


begin

-- cnext <= '0';

GEN:

for i in  0 to width-1 generate

genlsb : if i = 0 generate

	fazero: m9_fulladd

	port map (
					cin => '0',
					a => a(i),
					b => b(i),
					cout => cout_null(i),
					sum => s_null(i)
				 );

	faone: m9_fulladd
	port map (
					cin => '1',
					a => a(i),
					b => b(i),
					cout => cout_eins(i),
					sum => s_eins(i)
				 );

cnext(i) <= cout_null(i) when cin = '0' else cout_eins(i);

sum_ergebnis(i) <= s_null(i) when cin = '0' else s_eins(i);



end generate;

 genmid: if (i > 0) and (i < width -1)

 generate

 fazero: m9_fulladd

	port map (
					cin => '0',
					a => a(i),
					b => b(i),
					cout => cout_null(I),
					sum => s_null(i)
				 );

	faone: m9_fulladd
	port map (
					cin => '1',
					a => a(i),
					b => b(i),
					cout => cout_eins(i),
					sum => s_eins(i)
				 );

cnext(i) <= cout_null(i) when cnext(i-1) = '0' else cout_eins(i);

sum_ergebnis(i) <= s_null(i) when cnext(i-1) = '0' else s_eins(i);

end generate;

genmsb: if i = (width -1)

generate

 fazero: m9_fulladd

	port map (
					cin => '0',
					a => a(i),
					b => b(i),
					cout => cout_null(i),
					sum => s_null(i)
				 );

	faone: m9_fulladd
	port map (
					cin => '1',
					a => a(i),
					b => b(i),
					cout => cout_eins(i),
					sum => s_eins(i)
				 );

cout <= cout_null(i) when cnext(i-1) = '0' else cout_eins(i);

sum_ergebnis(i) <= s_null(i) when cnext(i-1) = '0' else s_eins(i);


end generate;




 --cnext <= cout_null when cnext = '0' else cout_eins;

-- sum_ergebnis <= s_null when cnext = '0' else s_eins;





end generate;




end Behavioral;