BIN_TO_7SEG

DEF NOT
PORT IN A
PORT OUT Z
INST N2 NAND A A Z
ENDDEF

DEF AND
PORT IN A
PORT IN B
PORT OUT Z
NET NAB
INST N1 NAND A B NAB
INST N2 NOT NAB Z
ENDDEF


DEF MUX21
PORT IN L0
PORT IN L1
PORT IN S
PORT IN NS
PORT OUT Z
NET F
NET G

INST N2 NAND L0 NS F
INST N3 NAND L1 S G
INST N4 NAND F G Z
ENDDEF

DEF MUX41
PORT IN L0
PORT IN L1
PORT IN L2
PORT IN L3
PORT IN S0
PORT IN S1
PORT IN NS0
PORT IN NS1
PORT OUT Z
NET E
NET F

INST N1 MUX21 L0 L1 S0 NS0 E
INST N2 MUX21 L2 L3 S0 NS0 F
INST N3 MUX21 E F S1 NS1 Z
ENDDEF

DEF MUX81
PORT IN L0
PORT IN L1
PORT IN L2
PORT IN L3
PORT IN L4
PORT IN L5
PORT IN L6
PORT IN L7
PORT IN S0
PORT IN S1
PORT IN S2
PORT IN NS0
PORT IN NS1
PORT IN NS2
PORT OUT Z
NET E
NET F

INST N1 MUX41 L0 L1 L2 L3 S0 S1 NS0 NS1 E
INST N2 MUX41 L4 L5 L6 L7 S0 S1 NS0 NS1 F
INST N3 MUX21 E F S2 NS2 Z
ENDDEF

DEF MUXX7
PORT IN S0
PORT IN S1
PORT IN S2
PORT IN S3
PORT OUT A
PORT OUT B
PORT OUT C
PORT OUT D
PORT OUT E
PORT OUT F
PORT OUT G

NET NS0
NET NS1
NET NS2
NET NS3

#these nets are to simplify out all
#the mux21's that contain true or false
NET NST1
NET NST
NET ST1
NET ST
NET TNS1
NET TNS
NET TS1
NET TS
NET NSF
NET FNS
NET SF
NET SNS1
NET SNS2
NET SNS
NET NSS1
NET NSS2
NET NSS
NET TST1
NET TST
NET TSF1
NET TSF
NET B2
NET TNSS1
NET TNSS
NET E1
NET F1
NET G1
NET TRST1
NET TRST
NET NSTT1
NET NSTT
NET TNST1
NET TNST

INST NS0 NOT S0 NS0
INST NS1 NOT S1 NS1
INST NS2 NOT S2 NS2
INST NS3 NOT S3 NS3

INST K NAND NS0  NS1 NST1
INST NST  NAND NST1 NS1 NST

INST ST1 NAND S0  NS1 ST1
INST ST  NAND ST1 NS1 ST

INST TNS1 NAND NS0  S1 TNS1
INST TNS  NAND TNS1 S1 TNS

INST TS1 NAND S0  S1 TS1
INST TS  NAND TS1 S1 TS

INST TST1 NAND TS   NS2 TST1
INST TST  NAND TST1 NS2 TST

INST NSF AND NS0 NS1 NSF
INST FNS AND NS0 S1 FNS
INST SF  AND S0  NS1 SF

INST NSS1 NAND NS0 NS1 NSS1
INST NSS2 NAND S0 S1 NSS2
INST NSS NAND NSS1 NSS2 NSS

INST SNS1 NAND S0 NS1 SNS1
INST SNS2 NAND NS0 S1 SNS2
INST SNS NAND SNS1 SNS2 SNS

INST TSF1 NAND SF   S2 TSF1
INST TSF  NAND TSF1 S2 TSF

INST TRST1 NAND ST   S2 TRST1
INST TRST  NAND TRST1 S2 TRST

INST TNSS1 NAND NSS   S2 TNSS1
INST TNSS  NAND TNSS1 S2 TNSS

INST NSTT1 NAND NST   NS2 NSTT1
INST NSTT  NAND NSTT1 NS2 NSTT

INST TNST1 NAND NST   S2 TNST1
INST TNST  NAND TNST1 S2 TNST

INST A MUX41 NST ST TNS NST S2 S3 NS2 NS3 A

INST B2 MUX21 TNS SF S2 NS2 B2
INST B MUX21 TNSS B2 S3 NS3 B

INST C MUX21 TST TSF S3 NS3 C
INST D MUX41 NST SNS TS TNS S2 S3 NS2 NS3 D

INST E1 MUX21 NS0 FNS S2 NS2 E1
INST E MUX21 E1 NSTT  S3 NS3 E

INST F1 MUX21 NSF TNS S2 NS2 F1
INST F MUX21 F1 TNST  S3 NS3 F

INST G1 MUX21 S1 TNS S2 NS2 G1
INST G MUX21 G1 TRST  S3 NS3 G
ENDDEF

DEF BIN_TO_7SEG
PORT IN BIN<3:0>
PORT OUT A
PORT OUT B
PORT OUT C
PORT OUT D
PORT OUT E
PORT OUT F
PORT OUT G

INST B MUXX7 BIN<0> BIN<1> BIN<2> BIN<3> A B C D E F G
ENDDEF

DEF TOP
  NET BIN<3:0>
  NET A
  NET B
  NET C
  NET D
  NET E
  NET F
  NET G
  INST BIN_TO_7SEG BIN_TO_7SEG BIN<3:0> A B C D E F G
  INST TEST BIN_TO_7SEG_TEST BIN<3:0> A B C D E F G
  INST OUTBIN IO_OUT8 false,false,false,false,BIN<3:0>
  INST OUT7SEG IO_OUT7SEG A B C D E F G
ENDDEF