"on_SB_LUT4_I1_2_O": {
          "hide_name": 0,
          "bits": [ 122, 101, 97 ],
          "attributes": {
            "force_downto": "00000000000000000000000000000001",
            "src": "/opt/openfpga/bin/../share/yosys/ice40/cells_map.v:6.21-6.22"
          }
        },

------
Seems to be a "replica" of the input bits to that LUT: but I'm not sure why it deserves a label in the graph ...

        "timer_tick_SB_LUT4_I3_3": {
          "hide_name": 0,
          "type": "SB_LUT4",
          "parameters": {
            "LUT_INIT": "0000111111001100"
          },
          "attributes": {
            "module_not_derived": "00000000000000000000000000000001",
            "src": "/opt/openfpga/bin/../share/yosys/ice40/cells_map.v:22.34-23.52"
          },
          "port_directions": {
            "I0": "input",
            "I1": "input",
            "I2": "input",
            "I3": "input",
            "O": "output"
          },
          "connections": {
            "I0": [ "0" ],
            "I1": [ 122 ],
            "I2": [ 101 ],
            "I3": [ 97 ],
            "O": [ 113 ]
          }
        },