module zad3(
    input [0:0] KEY,
    input CLOCK_50,
    output [0:6] HEX0);

    wire [3:0] out;
    counter_mod_M(KEY[0],CLOCK_50,out);
    decoder_hex_16(out,HEX0);

endmodule

module counter_mod_M
    #(parameter M=10)
    (input aclr, clk,
    output [3:0] h);

    localparam N=clogb2(M-1);
    function integer clogb2(input [31:0] v);
    for(clogb2=0;v>0;clogb2=clogb2+1)
        v=v>>1;
    endfunction


    wire clockTact;

    reg [N-1:0] Q;
    assign h=Q;

    counter_to_make_delay ex0(clk, aclr, clockTact);

    always@(posedge clockTact, negedge aclr)
        if(!aclr) Q<=1'd0;
        else
            begin
                if(Q==M-1) Q<=1'd0;
                else Q<=Q+1;
            end

endmodule

module counter_to_make_delay(
    input clk, aclr,
    output reg clockTact);

    reg [25:0] i;

    always@(posedge clk, negedge aclr)
        if(!aclr)
            begin
                i<=0;
                clockTact<=0;
            end
        else
            begin
                if(i==3)
                    begin
                        i<=0;
                        clockTact<=1;
                    end
                else
                    begin
                        i<=i+1;
                        clockTact<=0;
                    end
            end

endmodule