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Oct 19th, 2024
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  1. [146]HELLO! BOOT0 is starting!
  2. [149]BOOT0 commit : d21a737
  3. [151]set pll start
  4. [153]periph0 has been enabled
  5. [156]set pll end
  6. [158]board init ok
  7. [160]DRAM only have internal ZQ!!
  8. [163]get_pmu_exist() = -1
  9. [165]ddr_efuse_type: 0x0
  10. [168][AUTO DEBUG] two rank and full DQ!
  11. [172]ddr_efuse_type: 0x0
  12. [175][AUTO DEBUG] rank 0 row = 15
  13. [178][AUTO DEBUG] rank 0 bank = 8
  14. [181][AUTO DEBUG] rank 0 page size = 2 KB
  15. [185][AUTO DEBUG] rank 1 row = 15
  16. [188][AUTO DEBUG] rank 1 bank = 8
  17. [191][AUTO DEBUG] rank 1 page size = 2 KB
  18. [195]rank1 config same as rank0
  19. [198]DRAM BOOT DRIVE INFO: V0.24
  20. [201]DRAM CLK = 792 MHz
  21. [203]DRAM Type = 3 (2:DDR2,3:DDR3)
  22. [206]DRAMC ZQ value: 0x7b7bfb
  23. [209]DRAM ODT value: 0x42.
  24. [211]ddr_efuse_type: 0x0
  25. [215]DRAM SIZE =1024 M
  26. [218]DRAM simple test OK.
  27. [220]dram size =1024
  28. [222]card no is 0
  29. [224]sdcard 0 line count 4
  30. [226][mmc]: mmc driver ver 2021-04-2 16:45
  31. [236][mmc]: Wrong media type 0x0
  32. [239][mmc]: ***Try SD card 0***
  33. [264][mmc]: HSSDR52/SDR25 4 bit
  34. [267][mmc]: 50000000 Hz
  35. [269][mmc]: 15193 MB
  36. [271][mmc]: ***SD/MMC 0 init OK!!!***
  37. [336]Loading boot-pkg Succeed(index=1).
  38. [340]Entry_name = opensbi
  39. [343]Entry_name = dtb
  40. [346]Entry_name = u-boot
  41. [349]Adding DRAM info to DTB.
  42. [355]Jump to second Boot.
  43.  
  44. OpenSBI v1.4
  45. ____ _____ ____ _____
  46. / __ \ / ____| _ \_ _|
  47. | | | |_ __ ___ _ __ | (___ | |_) || |
  48. | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
  49. | |__| | |_) | __/ | | |____) | |_) || |_
  50. \____/| .__/ \___|_| |_|_____/|____/_____|
  51. | |
  52. |_|
  53.  
  54. Platform Name : Sipeed Lichee RV Dock
  55. Platform Features : medeleg
  56. Platform HART Count : 1
  57. Platform IPI Device : aclint-mswi
  58. Platform Timer Device : aclint-mtimer @ 24000000Hz
  59. Platform Console Device : uart8250
  60. Platform HSM Device : sun20i-d1-ppu
  61. Platform PMU Device : thead,c900-pmu
  62. Platform Reboot Device : sunxi-wdt-reset
  63. Platform Shutdown Device : ---
  64. Platform Suspend Device : ---
  65. Platform CPPC Device : ---
  66. Firmware Base : 0x40000000
  67. Firmware Size : 327 KB
  68. Firmware RW Offset : 0x40000
  69. Firmware RW Size : 71 KB
  70. Firmware Heap Offset : 0x49000
  71. Firmware Heap Size : 35 KB (total), 2 KB (reserved), 9 KB (used), 23 KB (free)
  72. Firmware Scratch Size : 4096 B (total), 384 B (used), 3712 B (free)
  73. Runtime SBI Version : 2.0
  74.  
  75. Domain0 Name : root
  76. Domain0 Boot HART : 0
  77. Domain0 HARTs : 0*
  78. Domain0 Region00 : 0x0000000002500000-0x0000000002500fff M: (I,R,W) S/U: (R,W)
  79. Domain0 Region01 : 0x0000000014008000-0x000000001400bfff M: (I,R,W) S/U: ()
  80. Domain0 Region02 : 0x0000000014000000-0x0000000014007fff M: (I,R,W) S/U: ()
  81. Domain0 Region03 : 0x0000000040040000-0x000000004005ffff M: (R,W) S/U: ()
  82. Domain0 Region04 : 0x0000000040000000-0x000000004003ffff M: (R,X) S/U: ()
  83. Domain0 Region05 : 0x0000000010000000-0x0000000013ffffff M: (I,R,W) S/U: (R,W)
  84. Domain0 Region06 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
  85. Domain0 Next Address : 0x0000000040400000
  86. Domain0 Next Arg1 : 0x0000000040200000
  87. Domain0 Next Mode : S-mode
  88. Domain0 SysReset : yes
  89. Domain0 SysSuspend : yes
  90.  
  91. Boot HART ID : 0
  92. Boot HART Domain : root
  93. Boot HART Priv Version : v1.11
  94. Boot HART Base ISA : rv64imafdcvx
  95. Boot HART ISA Extensions : zicntr,zihpm
  96. Boot HART PMP Count : 8
  97. Boot HART PMP Granularity : 11 bits
  98. Boot HART PMP Address Bits: 38
  99. Boot HART MHPM Info : 12 (0x0003e3f8)
  100. Boot HART Debug Triggers : 0 triggers
  101. Boot HART MIDELEG : 0x0000000000020222
  102. Boot HART MEDELEG : 0x000000000000b109
  103. plic_irq_toggle irq:85,enable:1
  104. plic_irq_toggle irq:87,enable:1
  105. plic_irq_toggle irq:89,enable:1
  106. plic_irq_toggle irq:91,enable:1
  107. plic_irq_toggle irq:93,enable:1
  108. plic_irq_toggle irq:95,enable:1
  109. plic_irq_toggle irq:66,enable:1
  110. plic_irq_toggle irq:18,enable:1
  111. initialize rti_board_start:0 done
  112. initialize rt_hw_i2c_initplic_irq_toggle irq:25,enable:1
  113. [I/I2C] I2C bus [i2c0] registered
  114. :0 done
  115. initialize hal_hw_pin_init:0 done
  116. initialize rt_ktime_hrtimer_lock_init:0 done
  117. initialize rt_hw_backtrace_init:0 done
  118.  
  119. \ | /
  120. - RT - Thread Smart Operating System
  121. / | \ 5.0.2 build Oct 17 2024 18:30:10
  122. 2006 - 2022 Copyright by RT-Thread team
  123. do components initialization.
  124. initialize rti_board_end:0 done
  125. initialize dfs_init:0 done
  126. initialize rt_work_sys_workqueue_init:0 done
  127. initialize futex_system_init:0 done
  128. initialize pmutex_system_init:0 done
  129. initialize rt_hw_lcd_init[I/DBG] disp:[disp_probe 1078][DISP]disp_probe
  130.  
  131.  
  132. [I/DBG] disp:[disp_init 824]disp_init start
  133.  
  134.  
  135. [I/DBG] disp:[parser_disp_init_para 517]of_property_read screen0_output_format fail
  136.  
  137.  
  138. [I/DBG] disp:[parser_disp_init_para 524]of_property_read screen0_output_bits fail
  139.  
  140.  
  141. [I/DBG] disp:[parser_disp_init_para 531]of_property_read screen0_output_eotf fail
  142.  
  143.  
  144. [I/DBG] disp:[parser_disp_init_para 538]of_property_read screen0_output_cs fail
  145.  
  146.  
  147. [I/DBG] disp:[parser_disp_init_para 545]of_property_read screen0_output_dvi_hdmi fail
  148.  
  149.  
  150. [I/DBG] disp:[parser_disp_init_para 552]of_property_read screen0_output_range fail
  151.  
  152.  
  153. [I/DBG] disp:[parser_disp_init_para 559]of_property_read screen0_output_scan fail
  154.  
  155.  
  156. [I/DBG] disp:[parser_disp_init_para 566]of_property_read screen0_output_aspect_ratio fail
  157.  
  158.  
  159. [I/DBG] disp:[parser_disp_init_para 599]of_property_read screen1_output_mode fail
  160.  
  161.  
  162. [I/DBG] disp:[parser_disp_init_para 606]of_property_read screen1_output_format fail
  163.  
  164.  
  165. [I/DBG] disp:[parser_disp_init_para 614]of_property_read screen1_output_bits fail
  166.  
  167.  
  168. [I/DBG] disp:[parser_disp_init_para 622]of_property_read screen1_output_eotf fail
  169.  
  170.  
  171. [I/DBG] disp:[parser_disp_init_para 630]of_property_read screen1_output_cs fail
  172.  
  173.  
  174. [I/DBG] disp:[parser_disp_init_para 638]of_property_read screen1_output_dvi_hdmi fail
  175.  
  176.  
  177. [I/DBG] disp:[parser_disp_init_para 647]of_property_read screen1_output_range fail
  178.  
  179.  
  180. [I/DBG] disp:[parser_disp_init_para 655]of_property_read screen1_output_scan fail
  181.  
  182.  
  183. [I/DBG] disp:[parser_disp_init_para 664]read screen1_output_aspect_ratio fail
  184.  
  185.  
  186. [I/DBG] disp:[parser_disp_init_para 678]of_property_read disp_init.fb0_format fail
  187.  
  188.  
  189. [I/DBG] disp:[parser_disp_init_para 684]of_property_read fb0_width fail
  190.  
  191.  
  192. [I/DBG] disp:[parser_disp_init_para 690]of_property_read fb0_height fail
  193.  
  194.  
  195. [I/DBG] disp:[parser_disp_init_para 715]====display init para begin====
  196.  
  197.  
  198. [I/DBG] disp:[parser_disp_init_para 716]b_init:1
  199.  
  200.  
  201. [I/DBG] disp:[parser_disp_init_para 717]disp_mode:0
  202.  
  203.  
  204.  
  205. [I/DBG] disp:[parser_disp_init_para 719]output_type[0]:1
  206.  
  207.  
  208. [I/DBG] disp:[parser_disp_init_para 720]output_mode[0]:0
  209.  
  210.  
  211. [I/DBG] disp:[parser_disp_init_para 719]output_type[1]:0
  212.  
  213.  
  214. [I/DBG] disp:[parser_disp_init_para 720]output_mode[1]:0
  215.  
  216.  
  217. [I/DBG] disp:[parser_disp_init_para 723]buffer_num[0]:2
  218.  
  219.  
  220. [I/DBG] disp:[parser_disp_init_para 724]format[0]:0
  221.  
  222.  
  223. [I/DBG] disp:[parser_disp_init_para 725]fb_width[0]:0
  224.  
  225.  
  226. [I/DBG] disp:[parser_disp_init_para 726]fb_height[0]:0
  227.  
  228.  
  229. [I/DBG] disp:[parser_disp_init_para 723]buffer_num[1]:0
  230.  
  231.  
  232. [I/DBG] disp:[parser_disp_init_para 724]format[1]:0
  233.  
  234.  
  235. [I/DBG] disp:[parser_disp_init_para 725]fb_width[1]:0
  236.  
  237.  
  238. [I/DBG] disp:[parser_disp_init_para 726]fb_height[1]:0
  239.  
  240.  
  241. [I/DBG] disp:[parser_disp_init_para 728]====display init para end====
  242.  
  243.  
  244. [I/DBG] disp:[disp_init 842]mod 0, base=0x5000000, irq=0
  245.  
  246.  
  247. [I/DBG] disp:[disp_init 842]mod 1, base=0x5460000, irq=0
  248.  
  249.  
  250. [I/DBG] disp:[disp_init 842]mod 2, base=0x5461000, irq=106
  251.  
  252.  
  253. [I/DBG] disp:[disp_init 842]mod 3, base=0x5470000, irq=107
  254.  
  255.  
  256. [I/DBG] disp:[disp_init 842]mod 4, base=0x0, irq=0
  257.  
  258.  
  259. [I/DBG] disp:[disp_init 842]mod 5, base=0x0, irq=0
  260.  
  261.  
  262. [I/DBG] disp:[disp_init 842]mod 6, base=0x5450000, irq=108
  263.  
  264.  
  265. [I/DBG] disp:[disp_init 842]mod 7, base=0x0, irq=0
  266.  
  267.  
  268. [I/DBG] disp:[disp_init 842]mod 8, base=0x0, irq=0
  269.  
  270.  
  271. [I/DBG] disp:[disp_init 842]mod 9, base=0x0, irq=0
  272.  
  273.  
  274. [I/DBG] disp:[disp_init 842]mod 10, base=0x0, irq=0
  275.  
  276.  
  277. [I/DBG] disp:[disp_init 842]mod 11, base=0x0, irq=0
  278.  
  279.  
  280. [I/DBG] disp:[disp_init 842]mod 12, base=0x0, irq=0
  281.  
  282.  
  283. [I/DBG] disp:[disp_init 842]mod 13, base=0x0, irq=0
  284.  
  285.  
  286. [I/DBG] disp:[disp_init 842]mod 14, base=0x0, irq=0
  287.  
  288.  
  289. [I/DBG] disp:[de_rtmx_set_gld_reg_base 485]sel=0x0, addr=0x0x0000000040567cc8
  290.  
  291.  
  292. [I/DBG] disp:[de_rtmx_init 291]disp_sys_malloc memory ok(0x0x0000000040567d08) for video channel
  293.  
  294.  
  295. [I/DBG] disp:[de_rtmx_set_overlay_reg_base 524]sel=0x0, overlayer 0, addr=0x0x0000000040567d08
  296.  
  297.  
  298. [I/DBG] disp:[de_rtmx_set_overlay_reg_base 524]sel=0x0, overlayer 1, addr=0x0x0000000040568258
  299.  
  300.  
  301. [I/DBG] disp:[de_rtmx_set_bld_reg_base 502]sel=0, base=0x0x0000000040568788
  302.  
  303.  
  304. [I/DBG] disp:[de_vsu_set_reg_base 196]sel=0, chno=0, base=0x0x00000000405688b0
  305.  
  306.  
  307. [I/DBG] disp:[de_gsu_set_reg_base 160]sel=0, chno=0, base=0x0x0000000040569158
  308.  
  309.  
  310. [I/DBG] disp:[de_rtmx_set_gld_reg_base 485]sel=0x1, addr=0x0x00000000405693c0
  311.  
  312.  
  313. [I/DBG] disp:[de_rtmx_init 291]disp_sys_malloc memory ok(0x0x0000000040569400) for video channel
  314.  
  315.  
  316. [I/DBG] disp:[de_rtmx_set_overlay_reg_base 524]sel=0x1, overlayer 0, addr=0x0x0000000040569400
  317.  
  318.  
  319. [I/DBG] disp:[de_rtmx_set_bld_reg_base 502]sel=1, base=0x0x00000000405699a0
  320.  
  321.  
  322. [I/DBG] disp:[de_vsu_set_reg_base 196]sel=1, chno=0, base=0x0x0000000040569ac8
  323.  
  324.  
  325. [I/DBG] disp:[de_lti_init 69]sel 0, lti_base[0]=0x0x00000000051a4000
  326.  
  327.  
  328. [I/DBG] disp:[de_peak_init 79]sel 0, peak_base[0]=0x0x00000000051a6000
  329.  
  330.  
  331. [I/DBG] disp:[de_peak_set_reg_base 44]sel=0, chno=0, base=0x0x000000004056b490
  332.  
  333.  
  334. [I/DBG] disp:[de_ase_init 68]sel 0, ase_base[0]=0x0x00000000051a8000
  335.  
  336.  
  337. [I/DBG] disp:[de_ccsc_set_reg_base 48]sel=0, chno=0, base=0x0x000000004056b5e8
  338.  
  339.  
  340. [I/DBG] disp:[de_ccsc_init 212]sel0, Icsc_base[0]=0x0x00000000051a0040
  341.  
  342.  
  343. [I/DBG] disp:[de_icsc_set_reg_base 56]sel=0, chno=0, base=0x0x000000004056b658
  344.  
  345.  
  346. [I/DBG] disp:[de_ccsc_set_reg_base 48]sel=1, chno=0, base=0x0x000000004056b698
  347.  
  348.  
  349. [I/DBG] disp:[de_dcsc_init 177]sel 0, Dcsc_base=0x0x00000000051b0000
  350.  
  351.  
  352. [I/DBG] disp:[de_dcsc_set_reg_base 40]sel=0, base=0x0x000000004056b708
  353.  
  354.  
  355. [I/DBG] disp:[de_dcsc_init 177]sel 1, Dcsc_base=0x0x00000000052b0000
  356.  
  357.  
  358. [I/DBG] disp:[de_dcsc_set_reg_base 40]sel=1, base=0x0x000000004056b778
  359.  
  360.  
  361. [I/DBG] disp:[wb_ebios_set_reg_base 71]sel=0, base=0x0x0000000005010000
  362.  
  363.  
  364. [I/DBG] disp:[disp_init_lcd 2529]disp_init_lcd
  365.  
  366.  
  367. [I/DBG] disp:[disp_init_lcd 2598]total number of clk in dsi:1
  368.  
  369.  
  370. [I/DBG] disp:[disp_init_lcd 2600]lcd 0, irq_no=106, irq_no_dsi=108
  371.  
  372.  
  373. [I/DBG] disp:[lcd_clk_init 512]lcd 0 clk init
  374.  
  375.  
  376. [I/DBG] disp:[disp_init_mgr 1666]disp_init_mgr
  377.  
  378.  
  379. [I/DBG] disp:[disp_init_mgr 1698]mgr 0, 0x0x000000004056d778
  380.  
  381.  
  382. [I/DBG] disp:[disp_init_mgr 1698]mgr 1, 0x0x000000004056d8e0
  383.  
  384.  
  385. [I/DBG] disp:[disp_init_lyr 684]disp_init_lyr
  386.  
  387.  
  388. [I/DBG] disp:[disp_init_enhance 685]disp_init_enhance
  389.  
  390.  
  391. [I/DBG] disp:[disp_init_connections 421]disp_init_connections
  392.  
  393.  
  394. [I/DBG] disp:[disp_get_layer_1 121]disp0 layer0: 0,0,0
  395.  
  396.  
  397. [I/DBG] disp:[disp_get_layer_1 121]disp0 layer1: 0,0,1
  398.  
  399.  
  400. [I/DBG] disp:[disp_get_layer_1 121]disp0 layer2: 0,0,2
  401.  
  402.  
  403. [I/DBG] disp:[disp_get_layer_1 121]disp0 layer3: 0,0,3
  404.  
  405.  
  406. [I/DBG] disp:[disp_get_layer_1 121]disp0 layer4: 0,1,0
  407.  
  408.  
  409. [I/DBG] disp:[disp_get_layer_1 121]disp0 layer5: 0,1,1
  410.  
  411.  
  412. [I/DBG] disp:[disp_get_layer_1 121]disp0 layer6: 0,1,2
  413.  
  414.  
  415. [I/DBG] disp:[disp_get_layer_1 121]disp0 layer7: 0,1,3
  416.  
  417.  
  418. [I/DBG] disp:[disp_device_set_manager 22]device 0, mgr 0
  419.  
  420.  
  421. [I/DBG] disp:[disp_get_layer_1 121]disp1 layer8: 1,0,0
  422.  
  423.  
  424. [I/DBG] disp:[disp_get_layer_1 121]disp1 layer9: 1,0,1
  425.  
  426.  
  427. [I/DBG] disp:[disp_get_layer_1 121]disp1 layer10: 1,0,2
  428.  
  429.  
  430. [I/DBG] disp:[disp_get_layer_1 121]disp1 layer11: 1,0,3
  431.  
  432.  
  433. [I/DBG] disp:[disp_lcd_set_panel_funs 1963]lcd 0, driver_name cwu50, panel_name default_lcd
  434.  
  435.  
  436. [I/DBG] disp:[disp_get_lcd 78]disp 1 not support lcd output
  437.  
  438.  
  439. [I/DBG] disp:[disp_lcd_set_panel_funs 1963]lcd 0, driver_name cwu50, panel_name cwu50
  440.  
  441.  
  442. [I/DBG] disp:[bsp_disp_lcd_set_panel_funs 1505]panel driver cwu50 register
  443.  
  444.  
  445. [I/DBG] disp:[disp_get_lcd 78]disp 1 not support lcd output
  446.  
  447.  
  448. [I/DBG] disp:[disp_init 889]disp_init finish
  449.  
  450.  
  451. [I/DBG] disp:[disp_mgr_set_layer_config 1184]mgr0, config 1 layers
  452.  
  453.  
  454. [I/DBG] disp:[disp_mgr_set_layer_config 1191]layer:ch1, layer0, format=0, size=<720,1280>, crop=<0,0,720,1280>,frame=<720,1280>, en=1 addr[0x43800000,0x4384b000,0x4389600>
  455.  
  456.  
  457. [I/DBG] disp:[disp_get_layer 88]0,1,0, name=mgr0 chn1 lyr0
  458.  
  459.  
  460. [I/DBG] disp:[disp_lyr_save_and_dirty_check 473]layer:ch1, layer0, format=0, size=<720,1280>, crop=<0,0,720,1280>,frame=<720,1280>, en=1 addr[0x43800000,0x4384b000,0x4389>
  461.  
  462.  
  463. [I/DBG] disp:[disp_mgr_apply 1398]mgr 0 apply
  464.  
  465.  
  466. [I/DBG] disp:[bsp_disp_shadow_protect 691]sel=0, protect:1, cnt=1
  467.  
  468.  
  469. [I/DBG] disp:[de_al_lyr_apply 484]ch0 z 0 dis
  470.  
  471.  
  472. [I/DBG] disp:[de_al_lyr_apply 484]ch1 z 0 en
  473.  
  474.  
  475. [I/DBG] disp:[de_al_lyr_apply 487]pipe0 z 1 en
  476.  
  477.  
  478. [I/DBG] disp:[de_al_lyr_apply 487]pipe1 z 0 dis
  479.  
  480.  
  481. [I/DBG] disp:[de_al_lyr_apply 503]format[0]=0
  482.  
  483.  
  484. [I/DBG] disp:[de_calc_overlay_scaler_para 178]ovl_rect[0]=<0,0>
  485.  
  486.  
  487. [I/DBG] disp:[de_calc_overlay_scaler_para 179]bld_rect[0]=<0,0,0,0>
  488.  
  489.  
  490. [I/DBG] disp:[de_calc_ovl_coord 384]half_shift_xy=<20000,18,0>
  491.  
  492.  
  493. [I/DBG] disp:[de_calc_ovl_coord 384]half_shift_xy=<20000,18,0>
  494.  
  495.  
  496. [I/DBG] disp:[de_rtmx_calc_chnrect 1965]layernum=4, i=0
  497.  
  498.  
  499. [I/DBG] disp:[de_rtmx_calc_chnrect 1966]crop=<0,0,720,1280>
  500.  
  501.  
  502. [I/DBG] disp:[de_rtmx_calc_chnrect 1968]layer=<0,0,720,1280>
  503.  
  504.  
  505. [I/DBG] disp:[de_rtmx_calc_chnrect 1977]ovl_rect=<0,0,720,1280>
  506.  
  507.  
  508. [I/DBG] disp:[de_rtmx_calc_chnrect 1979]bld_rect=<0,0,720,1280>
  509.  
  510.  
  511. [I/DBG] disp:[de_calc_overlay_scaler_para 178]ovl_rect[1]=<720,1280>
  512.  
  513.  
  514. [I/DBG] disp:[de_calc_overlay_scaler_para 179]bld_rect[1]=<0,0,720,1280>
  515.  
  516.  
  517. [I/DBG] disp:[de_calc_overlay_scaler_para 185]fmt[0]=0, ovlw[0]=0,ovlh[0]=0, bld_rect[0].w=0, bld_rect[0].h=0
  518.  
  519.  
  520. [I/DBG] disp:[de_vsu_set_para 272]sel0, ch 0, en=0, in<0x0>,out<0x0>
  521.  
  522.  
  523. [I/DBG] disp:[de_al_lyr_apply 710]sel=0, pipe_rect[0]=<0,0,720,1280>
  524.  
  525.  
  526. [I/DBG] disp:[de_rtmx_set_route 1775]sel0, pno0, zorder1, route:0x0
  527.  
  528.  
  529. [I/DBG] disp:[de_rtmx_set_route 1778]addr=0x0x0000000040568808, reg=0x1
  530.  
  531.  
  532. [I/DBG] disp:[de_al_lyr_apply 710]sel=0, pipe_rect[1]=<0,0,0,0>
  533.  
  534.  
  535. [I/DBG] disp:[de_rtmx_set_route 1775]sel0, pno1, zorder0, route:0x1
  536.  
  537.  
  538. [I/DBG] disp:[de_rtmx_set_route 1778]addr=0x0x0000000040568808, reg=0x1
  539.  
  540.  
  541. [I/DBG] disp:[de_enhance_apply 203]disp 0, en=0, sharp=0
  542.  
  543.  
  544. [I/DBG] disp:[de_peak_enable 123]sel=0, chno=0, en=0
  545.  
  546.  
  547. [I/DBG] disp:[bsp_disp_shadow_protect 691]sel=0, protect:0, cnt=0
  548.  
  549.  
  550. :0 done
  551. initialize rt_hw_pwm_init:0 done
  552. initialize driver_sdmmc_inithal_sdc_create 0
  553. card_detect insert
  554. plic_irq_toggle irq:56,enable:1
  555. [I/DBG] disp:[start_work 757]sel=0, output_type=1, lcd_reg=1,hdmi_reg=0
  556.  
  557.  
  558. [I/DBG] disp:[disp_lcd_enable 1588]lcd 0
  559.  
  560.  
  561. [I/DBG] disp:[disp_mgr_enable 1485Initial card success. capacity :15193MB
  562. sdmmc bytes_per_secotr:200, sector count:1dacc00
  563. , sectnot found partition of mbr, construct sd0 at offset 8M, size:0xffffffffb5180000
  564. :0 done
  565. initialize null_device_init:0 done
  566. initialize random_device_init:0 done
  567. initialize urandom_device_init:0 done
  568. initialize zero_device_init:0 done
  569. initialize ptmx_register:0 done
  570. initialize critical_init:0 done
  571. initialize elm_init:0 done
  572. initialize rx_thread_init:0 done
  573. initialize fal_init_auto[D/FAL] (fal_flash_init:47) Flash device | sdcard0 | addr: 0x00000000 | len: 0xb5980000 | blk_size: 0x00000200 |initialized finis.
  574. [I/FAL] ==================== FAL partition table ====================
  575. [I/FAL] | name | flash_dev | offset | length |
  576. [I/FAL] -------------------------------------------------------------
  577. [I/FAL] | download | sdcard0 | 0x00800000 | 0x00800000 |
  578. [I/FAL] | easyflash | sdcard0 | 0x01000000 | 0x00100000 |
  579. [I/FAL] | filesystem | sdcard0 | 0x01100000 | 0x00c00000 |
  580. [I/FAL] =============================================================
  581. [I/FAL] RT-Thread Flash Abstraction Layer initialize success.
  582. :3 done
  583. initialize rt_posix_stdio_init:0 done
  584. initialize mnt_init:0 done
  585. initialize finsh_system_init:0 done
  586. Hello RISC-V
  587. r initial
  588. [I/DBG] disp:[disp_mgr_clk_enable 884]set DE rate to 300000000
  589.  
  590.  
  591. [I/DBG] disp:[disp_mgr_clk_enable 899]mgr 0 clk enable
  592.  
  593.  
  594. [I/DBG] disp:[__de_clk_enable 127]clk 1 reset enable
  595.  
  596.  
  597. [I/DBG] disp:[__de_clk_enable 138]clk 1 gate enable
  598.  
  599.  
  600. [I/DBG] disp:[__de_clk_enable 149]clk 1 mod enable
  601.  
  602.  
  603. [I/DBG] disp:[disp_mgr_enable 1519]output res: 720 x 1280, cs=516, range=1, interlace=0
  604.  
  605.  
  606. [I/DBG] disp:[disp_mgr_apply 1398]mgr 0 apply
  607.  
  608.  
  609. [I/DBG] disp:[bsp_disp_shadow_protect 691]sel=0, protect:1, cnt=1
  610.  
  611.  
  612. [I/DBG] disp:[de_dcsc_apply 72]sel=0, in_fmt=0, mode=0, out_fmt=0, mode=1, range=1
  613.  
  614.  
  615. [I/DBG] disp:[de_al_lyr_apply 484]ch0 z 0 dis
  616.  
  617.  
  618. [I/DBG] disp:[de_al_lyr_apply 484]ch1 z 0 en
  619.  
  620.  
  621. [I/DBG] disp:[de_al_lyr_apply 487]pipe0 z 1 en
  622.  
  623.  
  624. [I/DBG] disp:[de_al_lyr_apply 487]pipe1 z 0 dis
  625.  
  626.  
  627. [I/DBG] disp:[de_al_lyr_apply 503]format[0]=0
  628.  
  629.  
  630. [I/DBG] disp:[de_calc_overlay_scaler_para 178]ovl_rect[0]=<0,0>
  631.  
  632.  
  633. [I/DBG] disp:[de_calc_overlay_scaler_para 179]bld_rect[0]=<0,0,0,0>
  634.  
  635.  
  636. [I/DBG] disp:[de_calc_ovl_coord 384]half_shift_xy=<20000,18,0>
  637.  
  638.  
  639. [I/DBG] disp:[de_calc_ovl_coord 384]half_shift_xy=<20000,18,0>
  640.  
  641.  
  642. [I/DBG] disp:[de_rtmx_calc_chnrect 1965]layernum=4, i=0
  643.  
  644.  
  645. [I/DBG] disp:[de_rtmx_calc_chnrect 1966]crop=<0,0,720,1280>
  646.  
  647.  
  648. [I/DBG] disp:[de_rtmx_calc_chnrect 1968]layer=<0,0,720,1280>
  649.  
  650.  
  651. [I/DBG] disp:[de_rtmx_calc_chnrect 1977]ovl_rect=<0,0,720,1280>
  652.  
  653.  
  654. [I/DBG] disp:[de_rtmx_calc_chnrect 1979]bld_rect=<0,0,720,1280>
  655.  
  656.  
  657. [I/DBG] disp:[de_calc_overlay_scaler_para 178]ovl_rect[1]=<720,1280>
  658.  
  659.  
  660. [I/DBG] disp:[de_calc_overlay_scaler_para 179]bld_rect[1]=<0,0,720,1280>
  661.  
  662.  
  663. [I/DBG] disp:[de_calc_overlay_scaler_para 185]fmt[0]=0, ovlw[0]=0,ovlh[0]=0, bld_rect[0].w=0, bld_rect[0].h=0
  664.  
  665.  
  666. [I/DBG] disp:[de_vsu_set_para 272]sel0, ch 0, en=0, in<0x0>,out<0x0>
  667.  
  668.  
  669. [I/DBG] disp:[de_al_lyr_apply 710]sel=0, pipe_rect[0]=<0,0,720,1280>
  670.  
  671.  
  672. [I/DBG] disp:[de_rtmx_set_route 1775]sel0, pno0, zorder1, route:0x0
  673.  
  674.  
  675. [I/DBG] disp:[de_rtmx_set_route 1778]addr=0x0x0000000040568808, reg=0x1
  676.  
  677.  
  678. [I/DBG] disp:[de_al_lyr_apply 710]sel=0, pipe_rect[1]=<0,0,0,0>
  679.  
  680.  
  681. [I/DBG] disp:[de_rtmx_set_route 1775]sel0, pno1, zorder0, route:0x1
  682.  
  683.  
  684. [I/DBG] disp:[de_rtmx_set_route 1778]addr=0x0x0000000040568808, reg=0x1
  685.  
  686.  
  687. [I/DBG] disp:[bsp_disp_shadow_protect 691]sel=0, protect:0, cnt=0
  688.  
  689.  
  690. [I/DBG] disp:[disp_enhance_apply 123]disp_enhance_apply, screen 0
  691.  
  692.  
  693. [I/DBG] disp:[bsp_disp_shadow_protect 691]sel=0, protect:1, cnt=1
  694.  
  695.  
  696. [I/DBG] disp:[de_dcsc_apply 72]sel=0, in_fmt=0, mode=0, out_fmt=0, mode=1, range=1
  697.  
  698.  
  699. [I/DBG] disp:[de_enhance_apply 203]disp 0, en=0, sharp=0
  700.  
  701.  
  702. [I/DBG] disp:[de_peak_enable 123]sel=0, chno=0, en=0
  703.  
  704.  
  705. [I/DBG] disp:[bsp_disp_shadow_protect 691]sel=0, protect:0, cnt=0
  706.  
  707.  
  708. [I/DBG] disp:[disp_enhance_apply 123]disp_enhance_apply, screen 0
  709.  
  710.  
  711. [I/DBG] disp:[bsp_disp_shadow_protect 691]sel=0, protect:1, cnt=1
  712.  
  713.  
  714. [I/DBG] disp:[de_dcsc_apply 72]sel=0, in_fmt=0, mode=0, out_fmt=0, mode=1, range=1
  715.  
  716.  
  717. [I/DBG] disp:[de_enhance_apply 203]disp 0, en=1, sharp=0
  718.  
  719.  
  720. [I/DBG] disp:[de_peak_enable 123]sel=0, chno=0, en=0
  721.  
  722.  
  723. [I/DBG] disp:[bsp_disp_shadow_protect 691]sel=0, protect:0, cnt=0
  724.  
  725.  
  726. [I/DBG] disp:[disp_sys_register_irq 247]disp_sys_register_irq, irqNo=108, Handler=0x0x000000004045e9f8, pArg=0x0x000000004056b7e8
  727.  
  728.  
  729. plic_irq_toggle irq:108,enable:1
  730. [I/DBG] disp:[lcd_clk_config 666]disp_sys_clk_set_rate:dsi's 0 th clk with 148500000
  731.  
  732.  
  733. [W/DBG] disp:[lcd_clk_config 681]disp 0, clk: pll(372000000),clk(372000000),dclk(62000000) dsi_rate(62000000)
  734. clk real:pll(372000000),clk(372000000),dclk(93000000) dsi_rate(148500000)
  735.  
  736.  
  737. [I/DBG] disp:[cal_real_frame_period 591]lcd frame period:51587000
  738.  
  739.  
  740. [I/DBG] disp:[disp_al_lcd_cfg 835]lcd cfg ok!
  741.  
  742.  
  743. raoyiming +++ LCD_open_flow
  744. msh /[I/DBG] disp:[disp_lcd_pin_cfg 910]lcd 0 pin config, state on, 1
  745.  
  746.  
  747. <0>raoyiming +++ sunxi_lcd_gpio_set_value
  748. [I/DBG] disp:[disp_lcd_enable 1659]open flow:step 0 finish, to delay 100
  749.  
  750.  
  751. <0>raoyiming +++ LCD_panel_init
  752. [I/DBG] disp:[disp_lcd_enable 1659]open flow:step 1 finish, to delay 200
  753.  
  754.  
  755. [I/DBG] disp:[disp_lcd_enable 1659]open flow:step 2 finish, to delay 200
  756.  
  757.  
  758. [I/DBG] disp:[disp_sys_pwm_enable 693]period_ns = 1000000
  759.  
  760.  
  761. [I/DBG] disp:[disp_sys_pwm_enable 694]duty_ns = 195312
  762.  
  763.  
  764. [I/DBG] disp:[disp_sys_pwm_enable 695]polarity = 0
  765.  
  766.  
  767. [I/DBG] disp:[disp_sys_pwm_enable 696]channel = 2
  768.  
  769.  
  770. [I/DBG] disp:[disp_lcd_enable 1659]open flow:step 3 finish, to delay 0
  771.  
  772.  
  773. [I/DBG] disp:[start_work 757]sel=1, output_type=0, lcd_reg=0,hdmi_reg=0
  774.  
  775.  
  776. Mount "sd0p0" on "/" fail
  777. lcd_dra
  778. lcd_draw_point
  779. msh />lcd_draw_point 100 100
  780. lcd_draw_point
  781. Darw point is x:100,y:100
  782. msh />
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