module shift_reg_r(
    input in,
    input [3:0] data,
    input clk,sclr,sload,
    output [3:0] y,
    output CR);

    wire c1,c2,c3;

    FFD_sclr_sload d0(in,clk,sclr,sload,data[0],c1);
    FFD_sclr_sload d1(c1,clk,sclr,sload,data[1],c2);
    FFD_sclr_sload d2(c2,clk,sclr,sload,data[2],c3);
    FFD_sclr_sload d3(c3,clk,sclr,sload,data[3],CR);

    assign y={CR,c3,c2,c1};
endmodule


module FFD_sclr_sload(
    input D,clk,sclr,sload,data,
    output reg Q);

    always @(posedge clk)
        if(sclr) Q <= 0;
        else if(sload) Q <= data;
        else Q <= D;
endmodule

module FSM_with_shift_reg(
    input w,clk,
    output [3:0] Y1,Y0,
    output z);

    wire c0,c1;

    shift_reg_r ex1( w,4'b0,clk,~w,1'b0,Y1,c1);
    shift_reg_r ex0(~w,4'b0,clk, w,1'b0,Y0,c0);

    assign z = c0 | c1;
endmodule