module allenMux(z, a, b, c, control);
input [7:0]a, b, c;
wire [7:0] op1, op2, op3, op3p2, op4;
wire [7:0] z0, z1, z2, z3;
wire [7:0] o0, o1, o2, o3;
output[7:0] z;
input [1:0] control;
wire [1:0] controlI;

// operation 1
or op1[7:0](op1, a, b, c);
not op1Out[7:0](z0, op1);
// operation 2
and op2[7:0](op2, a, b, c);
not op2Out[7:0](z1, op2);
// operation 3
not op3[7:0](op3, a);
not op3p2[7:0](op3p2, c);
xor op3Out[7:0](z2, op3, b, op3p2);
// operation 4
and op4[7:0](op4, a, b);
xor op4Out[7:0](z3, op4, c);

not inverseControl[1:0](controlI, control);

and o0[7:0](o0, z0, controlI[1], controlI[0]);
and o1[7:0](o1, z1, controlI[1], control[0]);
and o2[7:0](o2, z2, control[1], controlI[0]);
and o3[7:0](o3, z3, control[1], control[0]);

or name[7:0](z, o0, o1, o2, o3);
endmodule