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Feb 16th, 2020
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  1. #!/usr/bin/env python3
  2.  
  3. # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
  4. # This file is Copyright (c) 2018-2019 David Shah <dave@ds0.me>
  5. # License: BSD
  6.  
  7. import argparse
  8.  
  9. from migen import *
  10. from migen.genlib.resetsync import AsyncResetSynchronizer
  11.  
  12. from litex.boards.platforms import pcmcia
  13.  
  14. from litex.build.lattice.trellis import trellis_args, trellis_argdict
  15.  
  16. from litex.soc.cores.clock import *
  17. from litex.soc.integration.soc_sdram import *
  18. from litex.soc.integration.builder import *
  19.  
  20. from litedram.modules import MT41J128M16
  21. from litedram.phy import ECP5DDRPHY
  22.  
  23.  
  24. # CRG ----------------------------------------------------------------------------------------------
  25.  
  26. class _CRG(Module):
  27.     def __init__(self, platform, sys_clk_freq):
  28.         self.clock_domains.cd_init    = ClockDomain()
  29.         self.clock_domains.cd_por     = ClockDomain(reset_less=True)
  30.         self.clock_domains.cd_sys     = ClockDomain()
  31.         self.clock_domains.cd_sys2x   = ClockDomain()
  32.         self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
  33.  
  34.         # # #
  35.  
  36.         self.stop = Signal()
  37.         #clkosc = Signal()
  38.  
  39.         # PLL and HDMI TX init
  40.         #self.platform.add_source("/home/claude/gateware/i2c_top.v")
  41.         #self.platform.add_source("/home/claude/litex/gateware/i2c_init.v")
  42.         #self.platform.add_source("/home/claude/litex/gateware/i2c_master.v")
  43.         sda = platform.request("sda")
  44.         scl = platform.request("scl")
  45.         self.specials += [
  46.             Instance("i2c_top",
  47.             io_sda=sda,
  48.             io_sdc=scl
  49.             )
  50.         ]
  51.         self.platform.add_source("/home/claude/gateware/i2c_top.v")
  52.  
  53.  
  54.         # Clk / Rst
  55.         clk100 = platform.request("clk100")
  56.         rst_n  = platform.request("rst_n")
  57.         platform.add_period_constraint(clk100, 1e9/25e6)
  58.  
  59.  
  60.         # Power on reset
  61.         por_count = Signal(16, reset=2**16-1)
  62.         por_done  = Signal()
  63.         self.comb += self.cd_por.clk.eq(ClockSignal())
  64.         self.comb += por_done.eq(por_count == 0)
  65.         self.sync.por += If(~por_done, por_count.eq(por_count - 1))
  66.  
  67.         # PLL
  68.         self.submodules.pll = pll = ECP5PLL()
  69.         pll.register_clkin(clk100, 25e6)
  70.         pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
  71.         pll.create_clkout(self.cd_init, 20.2e6)
  72.         self.specials += [
  73.             Instance("ECLKSYNCB",
  74.                 i_ECLKI = self.cd_sys2x_i.clk,
  75.                 i_STOP  = self.stop,
  76.                 o_ECLKO = self.cd_sys2x.clk),
  77.             Instance("CLKDIVF",
  78.                 p_DIV     = "2.0",
  79.                 i_ALIGNWD = 0,
  80.                 i_CLKI    = self.cd_sys2x.clk,
  81.                 i_RST     = self.cd_sys2x.rst,
  82.                 o_CDIVX   = self.cd_sys.clk),
  83.             #Instance("OSCG",
  84.             #   p_DIV     = "16",
  85.             #   o_OSC     = clkosc),
  86.  
  87.             AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n),
  88.             AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
  89.         ]
  90.  
  91. # BaseSoC ------------------------------------------------------------------------------------------
  92.  
  93. class BaseSoC(SoCSDRAM):
  94.     def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs):
  95.         platform = pcmcia.Platform(toolchain=toolchain)
  96.  
  97.         # SoCSDRAM ---------------------------------------------------------------------------------
  98.         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
  99.  
  100.         # CRG --------------------------------------------------------------------------------------
  101.         self.submodules.crg = _CRG(platform, sys_clk_freq)
  102.  
  103.         # DDR3 SDRAM -------------------------------------------------------------------------------
  104.         if not self.integrated_main_ram_size:
  105.             self.submodules.ddrphy = ECP5DDRPHY(
  106.                 platform.request("ddram"),
  107.                 sys_clk_freq=sys_clk_freq)
  108.             self.add_csr("ddrphy")
  109.             self.add_constant("ECP5DDRPHY", None)
  110.             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
  111.             sdram_module = MT41J128M16(sys_clk_freq, "1:2")
  112.             self.register_sdram(self.ddrphy,
  113.                 geom_settings   = sdram_module.geom_settings,
  114.                 timing_settings = sdram_module.timing_settings)
  115.  
  116. # Build --------------------------------------------------------------------------------------------
  117.  
  118. def main():
  119.     parser = argparse.ArgumentParser(description="LiteX SoC on PCMCIA")
  120.     parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
  121.         help='gateware toolchain to use, diamond (default) or  trellis')
  122.     builder_args(parser)
  123.     soc_sdram_args(parser)
  124.     trellis_args(parser)
  125.     parser.add_argument("--sys-clk-freq", default=75e6,
  126.                         help="system clock frequency (default=75MHz)")
  127.     args = parser.parse_args()
  128.  
  129.     cls = BaseSoC
  130.     soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
  131.     builder = Builder(soc, **builder_argdict(args))
  132.     builder_kargs = {}
  133.     if args.toolchain == "trellis":
  134.         builder_kargs == trellis_argdict(args)
  135.     builder.build(**builder_kargs)
  136.  
  137. if __name__ == "__main__":
  138.     main()
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