library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity CLA_module is
    Port ( a : in  STD_LOGIC_VECTOR (2 downto 0);
           b : in  STD_LOGIC_VECTOR (2 downto 0);
           Cin : in STD_LOGIC;
           Sum : out  STD_LOGIC_VECTOR (2 downto 0);
           Cout : out STD_LOGIC
           );
end CLA_module;

architecture Behavioral of CLA_module is
    signal P, G, Cint: std_logic_vector(2 downto 0);
begin
P <= a xor b;
G <= a and b;
Cint(0) <= Cin;
Cint(1) <= (Cin and P(0)) or G(0);
Cint(2) <= (Cin and P(0) and P(1)) or (G(0) and P(1)) or G(1);

Cout <= G(2) or (P(2) and G(1)) or (P(1) and P(2) and G(0)) or (P(2) and P(1) and Cin);
Sum <= P xor Cint;
end Behavioral;