module PWM(output reg data_out, input nreset, input clk, input [3:0]cmd);
reg [3:0] num;
always@(posedge clk) begin

if(nreset==0) begin
data_out<=0;
end
else begin

num<=num+1;
if(cmd<num)
data_out<=0;
else if(cmd==0)
data_out<=0;
else
data_out<=1;
end

end
endmodule