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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TestBench is
end TestBench;

architecture Struct of TestBench is

component  divfreq is
generic(N: integer range 0 to 32 := 8);
port (
clk    : in std_logic;
reset  : in std_logic;
div    : in UNSIGNED(N-1 downto 0);
w   : out std_logic);
end component;

component TestGen is
generic(N: integer range 0 to 32 := 8);
port (
clk    : out std_logic;
reset  : out std_logic;
div  : out UNSIGNED(N-1 downto 0));
end component;

signal treset, tclk, tw: std_logic;
signal tdiv:  UNSIGNED (7 downto 0);


begin
  DF: divfreq
  port map (reset=>treset, clk=>tclk, div=>tdiv, w=>tw);

  TG: TestGen
  port map (reset=>treset, clk=>tclk, div=>tdiv);

end Struct;