module SimpleFIFO #(
  parameter SIZE = 32,         // Size of each element in bits
  parameter DEPTH = 180,       // Depth of the FIFO
  parameter MT = 1'b0,   // Initial value to fill the FIFO with
  parameter DIVISOR = 28'd30000000
)(
  input clk,             // Clock input
  input wire r_input,           // r_input input
  input wire event_trig,  // Write enable input
  output reg led,
  output reg led2,
  output reg led3,
  output reg led4,
  output reg rgb1g,
  output reg trig =0           // counter trigger
);
  reg [63:0] count = 0;       // Declare count as a register
  reg [0:0] fifo[DEPTH-1:0];
  reg [27:0] head;                 // Head pointer
  reg [27:0] time_counter=28'd0;
  integer i;
  reg eventflag;
  reg resetflag;
  reg resetflag2;
//   Initialize FIFO pointers and fill all cells with MT
initial begin
    head = 28'd0;
    for (i = 0; i < DEPTH; i = i + 1) begin
      fifo[i] = MT;
    end
    time_counter=28'd0;
    count=0;
    trig=0;
end

always @(posedge clk)
begin
    eventflag <= event_trig;
    if (event_trig == 1 && eventflag == 0) begin
        fifo[head] <= 1'b1;
        led<=~led;
    end else begin
        if (time_counter % 125000 == 41667) begin
            count = 0;
        end else if (time_counter % 125000 == 0) begin
            for (i = 0; i < DEPTH; i = i + 1) begin
              if (fifo[i] != MT) begin
                count = count + 1;
                if (count>=3)begin trig<=1;end
              end
            end
        end else if (time_counter % 125000 == 83333) begin
            if (resetflag2 == 1) begin
                for (i = 0; i < DEPTH; i = i + 1) begin
                    fifo[i] = MT;
                end
                resetflag2 <=0;
            end
        end
        resetflag <= r_input;
        if (r_input == 1 && resetflag == 0    ) begin
            count=0;
            trig=0;
            resetflag2 <= 1;
        end
        if (head>DEPTH) begin
            led4<=~led4;
            head <= 32'b0;
        end else begin
                 time_counter <= time_counter + 28'd1;
                 if(time_counter>=(DIVISOR-1))begin
                    time_counter <= 28'd0;
                    led3<=~led3;
                    head <= (head + 1);
                end
            rgb1g <= (time_counter<DIVISOR>>1)?1'b1:1'b0;
            if (head == DEPTH) begin
                fifo[0] <= MT;
            end else begin
                fifo[head+1] <= MT;
            end
        end
    end
end
endmodule