Lab6

module seg_scan(clk, rst, seg_en, seg);
input  clk, rst;
output [3:0] seg_en;
output [7:0] seg;

wire scan_clk, count_clk;
wire [3:0] scan_code;
reg [31:0] div;
reg [15:0] count;
reg [3:0] seg_en;

always@(posedge clk, negedge rst)
begin
    if(!rst)
      div <= 32'b0;
    else
      div <= div + 1;
end

assign scan_clk  = div[16];  // 約5ms   250Hz scan period 20ms / 4(segs)
assign count_clk = div[17];  // 約10ms  100Hz

always@(posedge scan_clk, negedge rst) //low level to enable seg
begin
    if(!rst)
        seg_en <= 4'b1110 ;
    else
        seg_en <= !seg_en[0]?4'b1101:
                  !seg_en[1]?4'b1011:
                  !seg_en[2]?4'b0111:
                  4'b1110;
end


assign scan_code =  (seg_en == 4'b1110) ? (count[3:0]) :
                    (seg_en == 4'b1101) ? (count[7:4]) :
                    (seg_en == 4'b1011) ? (count[11:8]) :
                    (count[15:12]) ;

always@(posedge count_clk, negedge rst) //plus 6 to fix the BCD_code
begin
    if(!rst)
        count <= 0 ;
    else if(count[15:12]==9)
        count[15:12] <= count[15:12]+6;
    else if(count[11:8]==9)
        count[12:8] <= count[12:8]+6;
    else if(count[7:4]==9)
        count[8:4] <= count[8:4]+6;
    else if(count[3:0]==9)
        count[4:0] <= count[4:0]+6;
    else
        count <= count+1 ;

end

assign seg = (scan_code==0)?(8'b00000011):
             (scan_code==1)?(8'b10011111):
             (scan_code==2)?(8'b00100101):
             (scan_code==3)?(8'b00001101):
             (scan_code==4)?(8'b10011001):
             (scan_code==5)?(8'b01001001):
             (scan_code==6)?(8'b01000001):
             (scan_code==7)?(8'b00011011):
             (scan_code==8)?(8'b00000001):
             (8'b00001001);

endmodule