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Feb 16th, 2020
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  1. module testbench();
  2.  
  3. timeunit 10ns;
  4.  
  5. timeprecision 1ns;
  6.  
  7. logic clk=0;
  8. logic Reset, ClearA_LoadB, Run;
  9. //inputs
  10. logic [7:0] S;
  11. logic [7:0] B;
  12. //outputs
  13. logic [7:0] A;
  14. logic X;
  15.  
  16. always begin : CLOCK_GENERATION
  17. #1 Clk = ~Clk;
  18. end
  19.  
  20. initial begin: CLOCK_INITIALIZATION
  21. Clk = 0;
  22. end
  23.  
  24. // Testing begins here
  25. // The initial block is not synthesizable
  26. // Everything happens sequentially inside an initial block
  27. // as in a software program
  28. initial begin: TEST_VECTORS
  29. Reset = 1;
  30. S = 8'b00000111;
  31. ClearA_LoadB = 0;
  32. B = 8'b11000101;
  33. Execute = 0;
  34.  
  35. end
  36. endmodule
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