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  1. module rng(start, r_out);
  2. input start /* synthesis keep */;
  3. reg rout /* synthesis keep */;
  4. output r_out;
  5. wire n0 /* synthesis keep */;
  6. wire n1 /* synthesis keep */;
  7. wire n2 /* synthesis keep */;
  8. wire n3 /* synthesis keep */;
  9. wire n4 /* synthesis keep */;
  10. wire n5 /* synthesis keep */;
  11. mynot(n0,(r_out&start));
  12. mynot(n1,n0);
  13. mynot(n2,n1);
  14. mynot(n3,n2);
  15. mynot(n4,n3);
  16. mynot(n5,n4);
  17. mynot(r_out,n5);
  18. endmodule
  19.  
  20. module mynot(
  21.     input x,
  22.     output wire y
  23.     );
  24.     not(y,x);
  25. endmodule
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