`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/10/2023 05:13:54 PM
// Design Name:
// Module Name: Rx_fsm
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module Rx_fsm(
    input CLK50MHZ,
    input baud_tick,
    input FIFO_nFull,
    input RxD,
    input n_rst,
    output reg [7:0] sample,
    output reg Rx_Done
    );

    reg [5:0] state, next_state;
    reg [3:0] tick_no;
    reg [3:0] bit_no;
    parameter init = 6'b000001,
              wait7 = 6'b000010,
              wait16 = 6'b000100,
              sample_out = 6'b001000,
              add_bit = 6'b010000,
              done = 6'b100000;
    // State and next state register
    always@(posedge CLK50MHZ or negedge n_rst) begin
        if(!n_rst) begin
            state <= init;
        end
        else if(baud_tick) begin
            state <= next_state;
        end
        else begin
            state <= state;
        end
    end

     //Counter register
//    always@(posedge CLK50MHZ or negedge n_rst) begin
//        if(!n_rst) begin
//            tick_no <= 0;
//        end
//        else if(baud_tick) tick_no <= tick_no + 1;
//        else tick_no <= tick_no;
//    end

    always@(*) begin: next_state_logic
        case(state)
            init: begin
                tick_no = 0;
                bit_no = 0;
                if(!RxD) next_state = wait7;
                else next_state = init;
            end
            wait7: begin
                bit_no = 0;
                tick_no = tick_no + 1;
                if(tick_no == 8) begin
                    next_state = wait16;
                    tick_no = 0;
                end
                else next_state = wait7;
            end
            wait16: begin
                bit_no = bit_no;
                tick_no = tick_no + 1;
                if(tick_no == 16) begin
                    next_state = sample_out;
                    tick_no = 0;
                end
                else next_state = wait16;
            end
            sample_out: begin
                next_state = add_bit;
                tick_no = tick_no;
                bit_no = bit_no;
            end
            add_bit: begin
                bit_no = bit_no + 1;
                tick_no = 0;
                if(bit_no == 8) begin
                    next_state = done;
                    bit_no = 0;
                    tick_no = 0;
                end
                else next_state = wait16;
            end
            done: begin
                tick_no = 0;
                bit_no = 0;
                next_state = init;
            end
            default: begin
                next_state = init;
                tick_no = 0;
                bit_no = 0;
            end
        endcase
    end

    always@(state) begin: output_logic
        case(state)
            init: begin
                sample = 8'b0;
                Rx_Done = 1'b0;
            end
            wait7: begin
                sample = 8'b0;
                Rx_Done = 1'b0;
            end
            wait16: begin
                sample = 8'b0;
                Rx_Done = 1'b0;
            end
            sample_out: begin
                sample[bit_no] = 1'b1;
                Rx_Done = 1'b0;
            end
            add_bit: begin
                sample = 8'b0;
                Rx_Done = 1'b0;
            end
            done: begin
                sample = 8'b0;
                Rx_Done = 1'b1;
            end
            default: begin
                sample = 8'b0;
                Rx_Done = 1'b0;
            end
        endcase
    end
endmodule