`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/06/2022 07:53:46 PM
// Design Name:
// Module Name: cfo_memory
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module cfo_memory #(parameter DATA_WIDTH = 16)
    (
        input  i_clk,
        input  i_EN,
        input  i_rstn,
        input  [DATA_WIDTH-1:0] i_I,
        input  [DATA_WIDTH-1:0] i_Q,
        output reg [DATA_WIDTH-1:0] o_I,
        output reg [DATA_WIDTH-1:0] o_Q,
        output reg o_valid
    );
reg [DATA_WIDTH-1:0] r_I [DATA_WIDTH-1:0];
reg [DATA_WIDTH-1:0] r_Q [DATA_WIDTH-1:0];
reg [3:0] r_inputAddress;
reg [3:0] r_outputAddress;
reg [3:0] r_delayedAddress;
reg [5:0] r_validCounter;
reg [5:0] r_validEst;

always@(posedge i_clk, negedge i_rstn)
    begin
        if(~i_rstn)
            begin
                r_inputAddress <= 4'd0;
                r_delayedAddress <= 4'd0;
                r_validCounter <= 6'd0;
            end
        else if(i_EN)
            begin
                r_inputAddress <= r_inputAddress+1;
                r_I[r_inputAddress] <= i_I;
                r_Q[r_inputAddress] <= i_Q;
                r_delayedAddress <= r_inputAddress;
                r_validCounter <= r_validEst;
            end
    end

always@(*)
    begin
        if(r_validCounter == 36)
            begin
                r_validEst = 6'd0;
            end
        else if(r_delayedAddress == 4'd15)
            begin
                r_validEst = r_validCounter + 1;
            end
    end



always@(posedge i_clk, negedge i_rstn)
    begin
        if(~i_rstn)
            begin
                r_outputAddress <= 4'b0000;
            end

        else if(~i_EN && r_delayedAddress == 15)
            begin
                r_outputAddress <= r_outputAddress+1;
                o_I <= r_I[r_outputAddress];
                o_Q <= r_Q[r_outputAddress];
            end
    end

 always@(posedge i_clk, negedge i_rstn)
    begin
        if(~i_rstn)
            begin
                o_valid <= 1'b0;
            end
        else if(i_EN && r_delayedAddress == 14)
            begin
                o_valid <= 1'b1;
            end
        else if (i_EN && r_delayedAddress == 15)
            begin
                 o_valid <= 1'b0;
            end

   end
endmodule