-- Lab1 for FPGA course
library ieee;
use ieee.std_logic_1164.all;

entity lab1 is
-- btns are inputs of the circuit
-- leds are outputs of the circuit
port (
    btn : in std_logic_vector(3 downto 0);
    led : out std_logic_vector(3 downto 0)
);
end lab1;

architecture rtl of lab1 is
    -- intermediate signals
    signal l0, l1 : std_logic := '0';
begin

    -- concurrent assignments
    --   order does not matter
    led(0) <= not btn(0);
    l0 <= btn(1) and (not btn(2));
    led(1) <= l0;
    l1 <= btn(2) and btn(3);
    led(2) <= l1;
    led(3) <= l0 or l1;

end rtl;