module SRLatch(set,reset,reset1,q);
	input set, reset,reset1;
	output q;
	wire q_;
	nand n1(q,set,q_);
	nand n2(q_,reset,q,reset1);
endmodule

module DLatch(data,clk,reset,q);
	input data,clk,reset;
	output q;
	wire w1,w2,w3,reset1;

	not n3(reset1,reset);
	not n4(w3,data);

	nand n1(w1,data,clk);
	nand n2(w2,w3,clk);

	SRLatch sr(w1,w2,reset1,q);
endmodule


module DFlipFlop(Q,Q_,D,clk,reset_);
	output Q,Q_;
	input D,clk,reset_;
	wire D_,set,reset;

	not(D_,D);
	nand(set,D,clk);
	nand(reset,clk,D_);
	SRLatch sr(set,reset,reset_,Q);
	not(Q_,Q);


endmodule


module testbed;
	reg A,clk;
	wire A_fromMemory,Abar_fromMemory;


	DFlipFlop aa(A_fromMemory,Abar_fromMemory,A,clk,1'b0);

	initial
	begin
		$display("A=%d A_fromMemory=%d",A,A_fromMemory);
		#5 A=1'b1;
		#5 $display("A=%d A_fromMemory=%d",A,A_fromMemory);
		#5 clk=1'b1;
		#5 $display("A=%d A_fromMemory=%d",A,A_fromMemory);
	end
endmodule