Manioc

cu

Nov 22nd, 2018
635
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  1. // DESCRIPTION: Verilator: Systemverilog example module
  2. // with interface to switch buttons, LEDs, LCD and register display
  3.  
  4. parameter NINSTR_BITS = 32;
  5. parameter NBITS_TOP = 8, NREGS_TOP = 32;
  6. module top(input  logic clk_2,
  7.            input  logic [NBITS_TOP-1:0] SWI,
  8.            output logic [NBITS_TOP-1:0] LED,
  9.            output logic [NBITS_TOP-1:0] SEG,
  10.            output logic [NINSTR_BITS-1:0] lcd_instruction,
  11.            output logic [NBITS_TOP-1:0] lcd_registrador [0:NREGS_TOP-1],
  12.            output logic [NBITS_TOP-1:0] lcd_pc, lcd_SrcA, lcd_SrcB,
  13.              lcd_ALUResult, lcd_Result, lcd_WriteData, lcd_ReadData,
  14.            output logic lcd_MemWrite, lcd_Branch, lcd_MemtoReg, lcd_RegWrite);
  15.  
  16.  
  17.   logic [1:0] clk_1;
  18.   logic [1:0] tempo;
  19.   always_ff @(posedge clk_2) begin
  20.     clk_1 <= clk_1 + 1;
  21.   end
  22.  
  23.   enum logic [1:0] {
  24.     base,
  25.     step1,
  26.     step2
  27.   } state;
  28.  
  29.   logic reset, painel, rede, sol;
  30.   logic [4:0] ligado, desligado;
  31.   always_comb begin
  32.     reset <= SWI[0];
  33.     sol <= SWI[1];
  34.   end
  35.  
  36.   always_ff @(posedge clk_1[1] or posedge reset) begin
  37.     if(reset) begin
  38.       state <= base;
  39.       painel <= 0;
  40.       rede <= 0;
  41.       ligado <= 0;
  42.       desligado <= 0;
  43.     end
  44.     else begin
  45.       tempo <= tempo + 1;
  46.       if(sol) begin
  47.         ligado <= ligado + 1;
  48.         desligado <= 0;
  49.       end else begin
  50.         desligado <= desligado + 1;
  51.         ligado <= 0;
  52.       end
  53.  
  54.       unique case(state)
  55.         base:
  56.           if(ligado) painel <= painel^1;
  57.           else if(desligado == 2) state <= step1;
  58.         step1:
  59.           if(ligado == 1) painel <= 1;
  60.           else if(ligado == 2) begin
  61.             state <= base;
  62.             painel <= 0;
  63.           end
  64.           else if(desligado == 3) state <= step2;
  65.         step2:
  66.           if(ligado == 1) begin
  67.             painel <= 1;
  68.             rede <= 0;
  69.           end
  70.           else if(ligado == 3) begin
  71.             state <= base;
  72.             painel <= 0;
  73.           end
  74.           else if(desligado > 3) rede <= 1;
  75.  
  76.       endcase
  77.     end
  78.   end
  79.   always_comb begin
  80.     LED[7] <= clk_1[1];
  81.     LED[0] <= painel;
  82.     LED[1] <= rede;
  83.     LED[6:5] <= tempo;
  84.   end
  85. endmodule
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