cu

// DESCRIPTION: Verilator: Systemverilog example module
// with interface to switch buttons, LEDs, LCD and register display

parameter NINSTR_BITS = 32;
parameter NBITS_TOP = 8, NREGS_TOP = 32;
module top(input  logic clk_2,
           input  logic [NBITS_TOP-1:0] SWI,
           output logic [NBITS_TOP-1:0] LED,
           output logic [NBITS_TOP-1:0] SEG,
           output logic [NINSTR_BITS-1:0] lcd_instruction,
           output logic [NBITS_TOP-1:0] lcd_registrador [0:NREGS_TOP-1],
           output logic [NBITS_TOP-1:0] lcd_pc, lcd_SrcA, lcd_SrcB,
             lcd_ALUResult, lcd_Result, lcd_WriteData, lcd_ReadData,
           output logic lcd_MemWrite, lcd_Branch, lcd_MemtoReg, lcd_RegWrite);


  logic [1:0] clk_1;
  logic [1:0] tempo;
  always_ff @(posedge clk_2) begin
    clk_1 <= clk_1 + 1;
  end

  enum logic [1:0] {
    base,
    step1,
    step2
  } state;

  logic reset, painel, rede, sol;
  logic [4:0] ligado, desligado;
  always_comb begin
    reset <= SWI[0];
    sol <= SWI[1];
  end

  always_ff @(posedge clk_1[1] or posedge reset) begin
    if(reset) begin
      state <= base;
      painel <= 0;
      rede <= 0;
      ligado <= 0;
      desligado <= 0;
    end
    else begin
      tempo <= tempo + 1;
      if(sol) begin
        ligado <= ligado + 1;
        desligado <= 0;
      end else begin
        desligado <= desligado + 1;
        ligado <= 0;
      end

      unique case(state)
        base:
          if(ligado) painel <= painel^1;
          else if(desligado == 2) state <= step1;
        step1:
          if(ligado == 1) painel <= 1;
          else if(ligado == 2) begin
            state <= base;
            painel <= 0;
          end
          else if(desligado == 3) state <= step2;
        step2:
          if(ligado == 1) begin
            painel <= 1;
            rede <= 0;
          end
          else if(ligado == 3) begin
            state <= base;
            painel <= 0;
          end
          else if(desligado > 3) rede <= 1;

      endcase
    end
  end
  always_comb begin
    LED[7] <= clk_1[1];
    LED[0] <= painel;
    LED[1] <= rede;
    LED[6:5] <= tempo;
  end
endmodule