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  1. [code]//
  2. // Source code for application to transmit image from ov7670 to PC via USB
  3. // Example for Arduino Uno/Nano
  4. // By Siarhei Charkes in 2015
  5. // http://privateblog.info
  6. //
  7.  
  8. #include <stdint.h>
  9. #include <avr/io.h>
  10. #include <util/twi.h>
  11. #include <util/delay.h>
  12. #include <avr/pgmspace.h>
  13.  
  14. #define F_CPU 16000000UL
  15. #define vga 0
  16. #define qvga 1
  17. #define qqvga 2
  18. #define yuv422 0
  19. #define rgb565 1
  20. #define bayerRGB 2
  21. #define camAddr_WR 0x42
  22. #define camAddr_RD 0x43
  23.  
  24. /* Registers */
  25. #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
  26. #define REG_BLUE 0x01 /* blue gain */
  27. #define REG_RED 0x02 /* red gain */
  28. #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
  29. #define REG_COM1 0x04 /* Control 1 */
  30. #define COM1_CCIR656 0x40 /* CCIR656 enable */
  31.  
  32. #define REG_BAVE 0x05 /* U/B Average level */
  33. #define REG_GbAVE 0x06 /* Y/Gb Average level */
  34. #define REG_AECHH 0x07 /* AEC MS 5 bits */
  35. #define REG_RAVE 0x08 /* V/R Average level */
  36. #define REG_COM2 0x09 /* Control 2 */
  37. #define COM2_SSLEEP 0x10 /* Soft sleep mode */
  38. #define REG_PID 0x0a /* Product ID MSB */
  39. #define REG_VER 0x0b /* Product ID LSB */
  40. #define REG_COM3 0x0c /* Control 3 */
  41. #define COM3_SWAP 0x40 /* Byte swap */
  42. #define COM3_SCALEEN 0x08 /* Enable scaling */
  43. #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
  44. #define REG_COM4 0x0d /* Control 4 */
  45. #define REG_COM5 0x0e /* All "reserved" */
  46. #define REG_COM6 0x0f /* Control 6 */
  47. #define REG_AECH 0x10 /* More bits of AEC value */
  48. #define REG_CLKRC 0x11 /* Clocl control */
  49. #define CLK_EXT 0x40 /* Use external clock directly */
  50. #define CLK_SCALE 0x3f /* Mask for internal clock scale */
  51. #define REG_COM7 0x12 /* Control 7 */ //REG mean address.
  52. #define COM7_RESET 0x80 /* Register reset */
  53. #define COM7_FMT_MASK 0x38
  54. #define COM7_FMT_VGA 0x00
  55. #define COM7_FMT_CIF 0x20 /* CIF format */
  56. #define COM7_FMT_QVGA 0x10 /* QVGA format */
  57. #define COM7_FMT_QCIF 0x08 /* QCIF format */
  58. #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
  59. #define COM7_YUV 0x00 /* YUV */
  60. #define COM7_BAYER 0x01 /* Bayer format */
  61. #define COM7_PBAYER 0x05 /* "Processed bayer" */
  62. #define REG_COM8 0x13 /* Control 8 */
  63. #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
  64. #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
  65. #define COM8_BFILT 0x20 /* Band filter enable */
  66. #define COM8_AGC 0x04 /* Auto gain enable */
  67. #define COM8_AWB 0x02 /* White balance enable */
  68. #define COM8_AEC 0x01 /* Auto exposure enable */
  69. #define REG_COM9 0x14 /* Control 9- gain ceiling */
  70. #define REG_COM10 0x15 /* Control 10 */
  71. #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
  72. #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
  73. #define COM10_HREF_REV 0x08 /* Reverse HREF */
  74. #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
  75. #define COM10_VS_NEG 0x02 /* VSYNC negative */
  76. #define COM10_HS_NEG 0x01 /* HSYNC negative */
  77. #define REG_HSTART 0x17 /* Horiz start high bits */
  78. #define REG_HSTOP 0x18 /* Horiz stop high bits */
  79. #define REG_VSTART 0x19 /* Vert start high bits */
  80. #define REG_VSTOP 0x1a /* Vert stop high bits */
  81. #define REG_PSHFT 0x1b /* Pixel delay after HREF */
  82. #define REG_MIDH 0x1c /* Manuf. ID high */
  83. #define REG_MIDL 0x1d /* Manuf. ID low */
  84. #define REG_MVFP 0x1e /* Mirror / vflip */
  85. #define MVFP_MIRROR 0x20 /* Mirror image */
  86. #define MVFP_FLIP 0x10 /* Vertical flip */
  87.  
  88. #define REG_AEW 0x24 /* AGC upper limit */
  89. #define REG_AEB 0x25 /* AGC lower limit */
  90. #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
  91. #define REG_HSYST 0x30 /* HSYNC rising edge delay */
  92. #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
  93. #define REG_HREF 0x32 /* HREF pieces */
  94. #define REG_TSLB 0x3a /* lots of stuff */
  95. #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
  96. #define REG_COM11 0x3b /* Control 11 */
  97. #define COM11_NIGHT 0x80 /* NIght mode enable */
  98. #define COM11_NMFR 0x60 /* Two bit NM frame rate */
  99. #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
  100. #define COM11_50HZ 0x08 /* Manual 50Hz select */
  101. #define COM11_EXP 0x02
  102. #define REG_COM12 0x3c /* Control 12 */
  103. #define COM12_HREF 0x80 /* HREF always */
  104. #define REG_COM13 0x3d /* Control 13 */
  105. #define COM13_GAMMA 0x80 /* Gamma enable */
  106. #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
  107. #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
  108. #define REG_COM14 0x3e /* Control 14 */
  109. #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
  110. #define REG_EDGE 0x3f /* Edge enhancement factor */
  111. #define REG_COM15 0x40 /* Control 15 */
  112. #define COM15_R10F0 0x00 /* Data range 10 to F0 */
  113. #define COM15_R01FE 0x80 /* 01 to FE */
  114. #define COM15_R00FF 0xc0 /* 00 to FF */
  115. #define COM15_RGB565 0x10 /* RGB565 output */
  116. #define COM15_RGB555 0x30 /* RGB555 output */
  117. #define REG_COM16 0x41 /* Control 16 */
  118. #define COM16_AWBGAIN 0x08 /* AWB gain enable */
  119. #define REG_COM17 0x42 /* Control 17 */
  120. #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
  121. #define COM17_CBAR 0x08 /* DSP Color bar */
  122. /*
  123. * This matrix defines how the colors are generated, must be
  124. * tweaked to adjust hue and saturation.
  125. *
  126. * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
  127. * They are nine-bit signed quantities, with the sign bit
  128. * stored in0x58.Sign for v-red is bit 0, and up from there.
  129. */
  130. #define REG_CMATRIX_BASE 0x4f
  131. #define CMATRIX_LEN 6
  132. #define REG_CMATRIX_SIGN 0x58
  133. #define REG_BRIGHT 0x55 /* Brightness */
  134. #define REG_CONTRAS 0x56 /* Contrast control */
  135. #define REG_GFIX 0x69 /* Fix gain control */
  136. #define REG_REG76 0x76 /* OV's name */
  137. #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
  138. #define R76_WHTPCOR 0x40 /* White pixel correction enable */
  139. #define REG_RGB444 0x8c /* RGB 444 control */
  140. #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
  141. #define R444_RGBX 0x01 /* Empty nibble at end */
  142. #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
  143. #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
  144. #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
  145. #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
  146. #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
  147. #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
  148. #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
  149. #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
  150. #define REG_BD60MAX 0xab /* 60hz banding step limit */
  151. #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
  152. #define REG_BLUE 0x01 /* blue gain */
  153. #define REG_RED 0x02 /* red gain */
  154. #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
  155. #define REG_COM1 0x04 /* Control 1 */
  156. #define COM1_CCIR656 0x40 /* CCIR656 enable */
  157. #define REG_BAVE 0x05 /* U/B Average level */
  158. #define REG_GbAVE 0x06 /* Y/Gb Average level */
  159. #define REG_AECHH 0x07 /* AEC MS 5 bits */
  160. #define REG_RAVE 0x08 /* V/R Average level */
  161. #define REG_COM2 0x09 /* Control 2 */
  162. #define COM2_SSLEEP 0x10 /* Soft sleep mode */
  163. #define REG_PID 0x0a /* Product ID MSB */
  164. #define REG_VER 0x0b /* Product ID LSB */
  165. #define REG_COM3 0x0c /* Control 3 */
  166. #define COM3_SWAP 0x40 /* Byte swap */
  167. #define COM3_SCALEEN 0x08 /* Enable scaling */
  168. #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
  169. #define REG_COM4 0x0d /* Control 4 */
  170. #define REG_COM5 0x0e /* All "reserved" */
  171. #define REG_COM6 0x0f /* Control 6 */
  172. #define REG_AECH 0x10 /* More bits of AEC value */
  173. #define REG_CLKRC 0x11 /* Clocl control */
  174. #define CLK_EXT 0x40 /* Use external clock directly */
  175. #define CLK_SCALE 0x3f /* Mask for internal clock scale */
  176. #define REG_COM7 0x12 /* Control 7 */
  177. #define COM7_RESET 0x80 /* Register reset */
  178. #define COM7_FMT_MASK 0x38
  179. #define COM7_FMT_VGA 0x00
  180. #define COM7_FMT_CIF 0x20 /* CIF format */
  181. #define COM7_FMT_QVGA 0x10 /* QVGA format */
  182. #define COM7_FMT_QCIF 0x08 /* QCIF format */
  183. #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
  184. #define COM7_YUV 0x00 /* YUV */
  185. #define COM7_BAYER 0x01 /* Bayer format */
  186. #define COM7_PBAYER 0x05 /* "Processed bayer" */
  187. #define REG_COM8 0x13 /* Control 8 */
  188. #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
  189. #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
  190. #define COM8_BFILT 0x20 /* Band filter enable */
  191. #define COM8_AGC 0x04 /* Auto gain enable */
  192. #define COM8_AWB 0x02 /* White balance enable */
  193. #define COM8_AEC 0x01 /* Auto exposure enable */
  194. #define REG_COM9 0x14 /* Control 9- gain ceiling */
  195. #define REG_COM10 0x15 /* Control 10 */
  196. #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
  197. #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
  198. #define COM10_HREF_REV 0x08 /* Reverse HREF */
  199. #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
  200. #define COM10_VS_NEG 0x02 /* VSYNC negative */
  201. #define COM10_HS_NEG 0x01 /* HSYNC negative */
  202. #define REG_HSTART 0x17 /* Horiz start high bits */
  203. #define REG_HSTOP 0x18 /* Horiz stop high bits */
  204. #define REG_VSTART 0x19 /* Vert start high bits */
  205. #define REG_VSTOP 0x1a /* Vert stop high bits */
  206. #define REG_PSHFT 0x1b /* Pixel delay after HREF */
  207. #define REG_MIDH 0x1c /* Manuf. ID high */
  208. #define REG_MIDL 0x1d /* Manuf. ID low */
  209. #define REG_MVFP 0x1e /* Mirror / vflip */
  210. #define MVFP_MIRROR 0x20 /* Mirror image */
  211. #define MVFP_FLIP 0x10 /* Vertical flip */
  212. #define REG_AEW 0x24 /* AGC upper limit */
  213. #define REG_AEB 0x25 /* AGC lower limit */
  214. #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
  215. #define REG_HSYST 0x30 /* HSYNC rising edge delay */
  216. #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
  217. #define REG_HREF 0x32 /* HREF pieces */
  218. #define REG_TSLB 0x3a /* lots of stuff */
  219. #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
  220. #define REG_COM11 0x3b /* Control 11 */
  221. #define COM11_NIGHT 0x80 /* NIght mode enable */
  222. #define COM11_NMFR 0x60 /* Two bit NM frame rate */
  223. #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
  224. #define COM11_50HZ 0x08 /* Manual 50Hz select */
  225. #define COM11_EXP 0x02
  226. #define REG_COM12 0x3c /* Control 12 */
  227. #define COM12_HREF 0x80 /* HREF always */
  228. #define REG_COM13 0x3d /* Control 13 */
  229. #define COM13_GAMMA 0x80 /* Gamma enable */
  230. #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
  231. #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
  232. #define REG_COM14 0x3e /* Control 14 */
  233. #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
  234. #define REG_EDGE 0x3f /* Edge enhancement factor */
  235. #define REG_COM15 0x40 /* Control 15 */
  236. #define COM15_R10F0 0x00 /* Data range 10 to F0 */
  237. #define COM15_R01FE 0x80 /* 01 to FE */
  238. #define COM15_R00FF 0xc0 /* 00 to FF */
  239. #define COM15_RGB565 0x10 /* RGB565 output */
  240. #define COM15_RGB555 0x30 /* RGB555 output */
  241. #define REG_COM16 0x41 /* Control 16 */
  242. #define COM16_AWBGAIN 0x08 /* AWB gain enable */
  243. #define REG_COM17 0x42 /* Control 17 */
  244. #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
  245. #define COM17_CBAR 0x08 /* DSP Color bar */
  246.  
  247. #define CMATRIX_LEN 6
  248. #define REG_BRIGHT 0x55 /* Brightness */
  249. #define REG_REG76 0x76 /* OV's name */
  250. #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
  251. #define R76_WHTPCOR 0x40 /* White pixel correction enable */
  252. #define REG_RGB444 0x8c /* RGB 444 control */
  253. #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
  254. #define R444_RGBX 0x01 /* Empty nibble at end */
  255. #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
  256. #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
  257. #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
  258. #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
  259. #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
  260. #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
  261. #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
  262. #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
  263. #define REG_BD60MAX 0xab /* 60hz banding step limit */
  264. #define MTX1 0x4f /* Matrix Coefficient 1 */
  265. #define MTX2 0x50 /* Matrix Coefficient 2 */
  266. #define MTX3 0x51 /* Matrix Coefficient 3 */
  267. #define MTX4 0x52 /* Matrix Coefficient 4 */
  268. #define MTX5 0x53 /* Matrix Coefficient 5 */
  269. #define MTX6 0x54 /* Matrix Coefficient 6 */
  270. #define REG_CONTRAS 0x56 /* Contrast control */
  271. #define MTXS 0x58 /* Matrix Coefficient Sign */
  272. #define AWBC7 0x59 /* AWB Control 7 */
  273. #define AWBC8 0x5a /* AWB Control 8 */
  274. #define AWBC9 0x5b /* AWB Control 9 */
  275. #define AWBC10 0x5c /* AWB Control 10 */
  276. #define AWBC11 0x5d /* AWB Control 11 */
  277. #define AWBC12 0x5e /* AWB Control 12 */
  278. #define REG_GFI 0x69 /* Fix gain control */
  279. #define GGAIN 0x6a /* G Channel AWB Gain */
  280. #define DBLV 0x6b
  281. #define AWBCTR3 0x6c /* AWB Control 3 */
  282. #define AWBCTR2 0x6d /* AWB Control 2 */
  283. #define AWBCTR1 0x6e /* AWB Control 1 */
  284. #define AWBCTR0 0x6f /* AWB Control 0 */
  285.  
  286. struct regval_list{
  287. uint8_t reg_num;
  288. uint16_t value;
  289. };
  290.  
  291. const struct regval_list qvga_ov7670[] PROGMEM = {
  292. { REG_COM14, 0x19 },
  293. { 0x72, 0x11 },
  294. { 0x73, 0xf1 },
  295.  
  296. { REG_HSTART, 0x16 },
  297. { REG_HSTOP, 0x04 },
  298. { REG_HREF, 0xa4 },
  299. { REG_VSTART, 0x02 },
  300. { REG_VSTOP, 0x7a },
  301. { REG_VREF, 0x0a },
  302.  
  303.  
  304. /* { REG_HSTART, 0x16 },
  305. { REG_HSTOP, 0x04 },
  306. { REG_HREF, 0x24 },
  307. { REG_VSTART, 0x02 },
  308. { REG_VSTOP, 0x7a },
  309. { REG_VREF, 0x0a },*/
  310. { 0xff, 0xff }, /* END MARKER */
  311. };
  312.  
  313. const struct regval_list yuv422_ov7670[] PROGMEM = {
  314. { REG_COM7, 0x0 }, /* Selects YUV mode */
  315. { REG_RGB444, 0 }, /* No RGB444 please */
  316. { REG_COM1, 0 },
  317. { REG_COM15, COM15_R00FF },
  318. { REG_COM9, 0x6A }, /* 128x gain ceiling; 0x8 is reserved bit */
  319. { 0x4f, 0x80 }, /* "matrix coefficient 1" */
  320. { 0x50, 0x80 }, /* "matrix coefficient 2" */
  321. { 0x51, 0 }, /* vb */
  322. { 0x52, 0x22 }, /* "matrix coefficient 4" */
  323. { 0x53, 0x5e }, /* "matrix coefficient 5" */
  324. { 0x54, 0x80 }, /* "matrix coefficient 6" */
  325. { REG_COM13, COM13_UVSAT },
  326. { 0xff, 0xff }, /* END MARKER */
  327. };
  328.  
  329. const struct regval_list ov7670_default_regs[] PROGMEM = {//from the linux driver
  330. { REG_COM7, COM7_RESET },
  331. { REG_TSLB, 0x04 }, /* OV */
  332. { REG_COM7, 0 }, /* VGA */
  333. /*
  334. * Set the hardware window. These values from OV don't entirely
  335. * make sense - hstop is less than hstart. But they work...
  336. */
  337. { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
  338. { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
  339. { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
  340.  
  341. { REG_COM3, 0 }, { REG_COM14, 0 },
  342. /* Mystery scaling numbers */
  343. { 0x70, 0x3a }, { 0x71, 0x35 },
  344. { 0x72, 0x11 }, { 0x73, 0xf0 },
  345. { 0xa2,/* 0x02 changed to 1*/1 }, { REG_COM10, 0x0 },
  346. /* Gamma curve values */
  347. { 0x7a, 0x20 }, { 0x7b, 0x10 },
  348. { 0x7c, 0x1e }, { 0x7d, 0x35 },
  349. { 0x7e, 0x5a }, { 0x7f, 0x69 },
  350. { 0x80, 0x76 }, { 0x81, 0x80 },
  351. { 0x82, 0x88 }, { 0x83, 0x8f },
  352. { 0x84, 0x96 }, { 0x85, 0xa3 },
  353. { 0x86, 0xaf }, { 0x87, 0xc4 },
  354. { 0x88, 0xd7 }, { 0x89, 0xe8 },
  355. /* AGC and AEC parameters. Note we start by disabling those features,
  356. then turn them only after tweaking the values. */
  357. { REG_COM8, COM8_FASTAEC | COM8_AECSTEP },
  358. { REG_GAIN, 0 }, { REG_AECH, 0 },
  359. { REG_COM4, 0x40 }, /* magic reserved bit */
  360. { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
  361. { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
  362. { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
  363. { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
  364. { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
  365. { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
  366. { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
  367. { REG_HAECC7, 0x94 },
  368. { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC },
  369. { 0x30, 0 }, { 0x31, 0 },//disable some delays
  370. /* Almost all of these are magic "reserved" values. */
  371. { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
  372. { 0x16, 0x02 }, { REG_MVFP, 0x07 },
  373. { 0x21, 0x02 }, { 0x22, 0x91 },
  374. { 0x29, 0x07 }, { 0x33, 0x0b },
  375. { 0x35, 0x0b }, { 0x37, 0x1d },
  376. { 0x38, 0x71 }, { 0x39, 0x2a },
  377. { REG_COM12, 0x78 }, { 0x4d, 0x40 },
  378. { 0x4e, 0x20 }, { REG_GFIX, 0 },
  379. /*{0x6b, 0x4a},*/{ 0x74, 0x10 },
  380. { 0x8d, 0x4f }, { 0x8e, 0 },
  381. { 0x8f, 0 }, { 0x90, 0 },
  382. { 0x91, 0 }, { 0x96, 0 },
  383. { 0x9a, 0 }, { 0xb0, 0x84 },
  384. { 0xb1, 0x0c }, { 0xb2, 0x0e },
  385. { 0xb3, 0x82 }, { 0xb8, 0x0a },
  386.  
  387. /* More reserved magic, some of which tweaks white balance */
  388. { 0x43, 0x0a }, { 0x44, 0xf0 },
  389. { 0x45, 0x34 }, { 0x46, 0x58 },
  390. { 0x47, 0x28 }, { 0x48, 0x3a },
  391. { 0x59, 0x88 }, { 0x5a, 0x88 },
  392. { 0x5b, 0x44 }, { 0x5c, 0x67 },
  393. { 0x5d, 0x49 }, { 0x5e, 0x0e },
  394. { 0x6c, 0x0a }, { 0x6d, 0x55 },
  395. { 0x6e, 0x11 }, { 0x6f, 0x9e }, /* it was 0x9F "9e for advance AWB" */
  396. { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
  397. { REG_RED, 0x60 },
  398. { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC | COM8_AWB },
  399.  
  400. /* Matrix coefficients */
  401. { 0x4f, 0x80 }, { 0x50, 0x80 },
  402. { 0x51, 0 }, { 0x52, 0x22 },
  403. { 0x53, 0x5e }, { 0x54, 0x80 },
  404. { 0x58, 0x9e },
  405.  
  406. { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
  407. { 0x75, 0x05 }, { REG_REG76, 0xe1 },
  408. { 0x4c, 0 }, { 0x77, 0x01 },
  409. { REG_COM13, /*0xc3*/0x48 }, { 0x4b, 0x09 },
  410. { 0xc9, 0x60 }, /*{REG_COM16, 0x38},*/
  411. { 0x56, 0x40 },
  412.  
  413. { 0x34, 0x11 }, { REG_COM11, COM11_EXP | COM11_HZAUTO },
  414. { 0xa4, 0x82/*Was 0x88*/ }, { 0x96, 0 },
  415. { 0x97, 0x30 }, { 0x98, 0x20 },
  416. { 0x99, 0x30 }, { 0x9a, 0x84 },
  417. { 0x9b, 0x29 }, { 0x9c, 0x03 },
  418. { 0x9d, 0x4c }, { 0x9e, 0x3f },
  419. { 0x78, 0x04 },
  420.  
  421. /* Extra-weird stuff. Some sort of multiplexor register */
  422. { 0x79, 0x01 }, { 0xc8, 0xf0 },
  423. { 0x79, 0x0f }, { 0xc8, 0x00 },
  424. { 0x79, 0x10 }, { 0xc8, 0x7e },
  425. { 0x79, 0x0a }, { 0xc8, 0x80 },
  426. { 0x79, 0x0b }, { 0xc8, 0x01 },
  427. { 0x79, 0x0c }, { 0xc8, 0x0f },
  428. { 0x79, 0x0d }, { 0xc8, 0x20 },
  429. { 0x79, 0x09 }, { 0xc8, 0x80 },
  430. { 0x79, 0x02 }, { 0xc8, 0xc0 },
  431. { 0x79, 0x03 }, { 0xc8, 0x40 },
  432. { 0x79, 0x05 }, { 0xc8, 0x30 },
  433. { 0x79, 0x26 },
  434. { 0xff, 0xff }, /* END MARKER */
  435. };
  436.  
  437.  
  438. void error_led(void){
  439. DDRB |= 32;//make sure led is output
  440. while (1){//wait for reset
  441. PORTB ^= 32;// toggle led
  442. _delay_ms(100);
  443. }
  444. }
  445.  
  446. void twiStart(void){
  447. TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN);//send start
  448. while (!(TWCR & (1 << TWINT)));//wait for start to be transmitted
  449. if ((TWSR & 0xF8) != TW_START)
  450. error_led();
  451. }
  452.  
  453. void twiWriteByte(uint8_t DATA, uint8_t type){
  454. TWDR = DATA;
  455. TWCR = _BV(TWINT) | _BV(TWEN);
  456. while (!(TWCR & (1 << TWINT))) {}
  457. if ((TWSR & 0xF8) != type)
  458. error_led();
  459. }
  460.  
  461. void twiAddr(uint8_t addr, uint8_t typeTWI){
  462. TWDR = addr;//send address
  463. TWCR = _BV(TWINT) | _BV(TWEN); /* clear interrupt to start transmission */
  464. while ((TWCR & _BV(TWINT)) == 0); /* wait for transmission */
  465. if ((TWSR & 0xF8) != typeTWI)
  466. error_led();
  467. }
  468.  
  469. void wrReg(uint8_t reg, uint8_t dat){
  470. //send start condition
  471. twiStart();
  472. twiAddr(camAddr_WR, TW_MT_SLA_ACK);
  473. twiWriteByte(reg, TW_MT_DATA_ACK);
  474. twiWriteByte(dat, TW_MT_DATA_ACK);
  475. TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);//send stop
  476. _delay_ms(1);
  477. }
  478.  
  479. static uint8_t twiRd(uint8_t nack){
  480. if (nack){
  481. TWCR = _BV(TWINT) | _BV(TWEN);
  482. while ((TWCR & _BV(TWINT)) == 0); /* wait for transmission */
  483. if ((TWSR & 0xF8) != TW_MR_DATA_NACK)
  484. error_led();
  485. return TWDR;
  486. }
  487. else{
  488. TWCR = _BV(TWINT) | _BV(TWEN) | _BV(TWEA);
  489. while ((TWCR & _BV(TWINT)) == 0); /* wait for transmission */
  490. if ((TWSR & 0xF8) != TW_MR_DATA_ACK)
  491. error_led();
  492. return TWDR;
  493. }
  494. }
  495.  
  496. uint8_t rdReg(uint8_t reg){
  497. uint8_t dat;
  498. twiStart();
  499. twiAddr(camAddr_WR, TW_MT_SLA_ACK);
  500. twiWriteByte(reg, TW_MT_DATA_ACK);
  501. TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);//send stop
  502. _delay_ms(1);
  503. twiStart();
  504. twiAddr(camAddr_RD, TW_MR_SLA_ACK);
  505. dat = twiRd(1);
  506. TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);//send stop
  507. _delay_ms(1);
  508. return dat;
  509. }
  510.  
  511. void wrSensorRegs8_8(const struct regval_list reglist[]){
  512. uint8_t reg_addr, reg_val;
  513. const struct regval_list *next = reglist;
  514. while ((reg_addr != 0xff) | (reg_val != 0xff)){
  515. reg_addr = pgm_read_byte(&next->reg_num);
  516. reg_val = pgm_read_byte(&next->value);
  517. wrReg(reg_addr, reg_val);
  518. next++;
  519. }
  520. }
  521.  
  522. void setColor(void){
  523. wrSensorRegs8_8(yuv422_ov7670);
  524. }
  525.  
  526. void setRes(void){
  527. wrReg(REG_COM3, 4); // REG_COM3 enable scaling
  528. wrSensorRegs8_8(qvga_ov7670);
  529. }
  530.  
  531. void camInit(void){
  532. wrReg(0x12, 0x80);
  533. _delay_ms(100);
  534. wrSensorRegs8_8(ov7670_default_regs);
  535. wrReg(REG_COM10, 32);//PCLK does not toggle on HBLANK.
  536. }
  537.  
  538. void arduinoUnoInut(void) {
  539. cli();//disable interrupts
  540.  
  541. /* Setup the 8mhz PWM clock
  542. * This will be on pin 11*/
  543. DDRB |= (1 << 3);//pin 11
  544. ASSR &= ~(_BV(EXCLK) | _BV(AS2));
  545. TCCR2A = (1 << COM2A0) | (1 << WGM21) | (1 << WGM20);
  546. TCCR2B = (1 << WGM22) | (1 << CS20);
  547. OCR2A = 0;//(F_CPU)/(2*(X+1))
  548. DDRC &= ~15;//low d0-d3 camera
  549. DDRD &= ~252;//d7-d4 and interrupt pins
  550. _delay_ms(3000);
  551.  
  552. //set up twi for 100khz
  553. TWSR &= ~3;//disable prescaler for TWI
  554. TWBR = 72;//set to 100khz
  555.  
  556. //enable serial
  557. UBRR0H = 0;
  558. UBRR0L = 1;//0 = 2M baud rate. 1 = 1M baud. 3 = 0.5M. 7 = 250k 207 is 9600 baud rate.
  559. UCSR0A |= 2;//double speed aysnc
  560. UCSR0B = (1 << RXEN0) | (1 << TXEN0);//Enable receiver and transmitter
  561. UCSR0C = 6;//async 1 stop bit 8bit char no parity bits
  562. }
  563.  
  564.  
  565. void StringPgm(const char * str){
  566. do{
  567. while (!(UCSR0A & (1 << UDRE0)));//wait for byte to transmit
  568. UDR0 = pgm_read_byte_near(str);
  569. while (!(UCSR0A & (1 << UDRE0)));//wait for byte to transmit
  570. } while (pgm_read_byte_near(++str));
  571. }
  572.  
  573. static void captureImg(uint16_t wg, uint16_t hg){
  574. uint16_t y, x;
  575.  
  576. StringPgm(PSTR("*RDY*"));
  577.  
  578. while (!(PIND & 8));//wait for high
  579. while ((PIND & 8));//wait for low
  580.  
  581. y = hg;
  582. while (y--){
  583. x = wg;
  584. //while (!(PIND & 256));//wait for high
  585. while (x--){
  586. while ((PIND & 4));//wait for low
  587. UDR0 = (PINC & 15) | (PIND & 240);
  588. while (!(UCSR0A & (1 << UDRE0)));//wait for byte to transmit
  589. while (!(PIND & 4));//wait for high
  590. while ((PIND & 4));//wait for low
  591. while (!(PIND & 4));//wait for high
  592. }
  593. // while ((PIND & 256));//wait for low
  594. }
  595. _delay_ms(100);
  596. }
  597.  
  598. void setup(){
  599. arduinoUnoInut();
  600. camInit();
  601. setRes();
  602. setColor();
  603. wrReg(0x11, 12);
  604. }
  605.  
  606.  
  607. void loop(){
  608. captureImg(320, 240);
  609. }
  610. [/code]
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