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// DESCRIPTION: Verilator: Systemverilog example module
// with interface to switch buttons, LEDs, LCD and register display

parameter NINSTR_BITS = 32;
parameter NBITS_TOP = 8, NREGS_TOP = 32;
module top(input  logic clk_2,
           input  logic [NBITS_TOP-1:0] SWI,
           output logic [NBITS_TOP-1:0] LED,
           output logic [NBITS_TOP-1:0] SEG,
           output logic [NINSTR_BITS-1:0] lcd_instruction,
           output logic [NBITS_TOP-1:0] lcd_registrador [0:NREGS_TOP-1],
           output logic [NBITS_TOP-1:0] lcd_pc, lcd_SrcA, lcd_SrcB,
             lcd_ALUResult, lcd_Result, lcd_WriteData, lcd_ReadData,
           output logic lcd_MemWrite, lcd_Branch, lcd_MemtoReg, lcd_RegWrite);

  logic counter;
  logic stop;
  logic reset;
  logic[1:0] chuva;

  // down clock

  logic[1:0] contPoucaOuNenhum;
  logic[1:0] contNenhum;
  logic[1:0] contDiluvio;

  logic[1:0] trava;

  logic [1:0] clock;
  always_ff @(posedge clk_2)
  begin
    clock += 1;
  end

  always_comb
  begin
    stop <= SWI[7];

    if(stop) begin
      counter <= counter;
    end
    else begin
      counter <= counter + 1;
    end


    LED[4] <= 1;
  end

endmodule