module fib(clk, reset, countt, out_fib_number);
// This module generates nth fibonacchi number, where n is the output of the count
    input clk, reset;
    reg[7:0] count;
    output [7:0]countt;
    output [7:0]out_fib_number;
    reg [7:0]prev, present;
    //state register
    always @(posedge clk)
    begin
        if(reset==1)
        begin
        count <= 1;
        end
        else
        begin
        count <= count + 1;
        end
    end

    //next state logic
    always @(posedge clk)
    begin
    case(count)
    1:begin
                prev <= 1; present <= 1;
        end
    default: begin
                present <= present + prev;
                prev <= present;
            end
    endcase
    end
    //output logic

    assign out_fib_number = present;
    assign countt = count;

endmodule