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Dom0_Device_Tree

Cheros
Apr 1st, 2020
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x02>;
  5. model = "Freescale S32G275";
  6. #size-cells = <0x02>;
  7. interrupt-parent = <0x01>;
  8. compatible = "fsl,s32g275-simu\0fsl,s32g275\0arm,vexpress,v2p-aarch64\0arm,vexpress";
  9.  
  10. flexcan@401B4000 {
  11. pinctrl-names = "default";
  12. pinctrl-0 = <0x0d>;
  13. clock-names = "per\0ipg";
  14. interrupts = <0x00 0x25 0x04 0x00 0x26 0x04 0x00 0x27 0x04 0x00 0x28 0x04>;
  15. clocks = <0x04 0x35 0x04 0x30>;
  16. compatible = "fsl,s32gen1-flexcan";
  17. status = "okay";
  18. interrupt-names = "state\0berr\0mb_0-7\0mb_8-127";
  19. reg = <0x00 0x401b4000 0x00 0xa000>;
  20. };
  21.  
  22. swt@4010C000 {
  23. clock-names = "swt";
  24. clocks = <0x04 0x01>;
  25. compatible = "fsl,s32gen1-wdt";
  26. status = "okay";
  27. reg = <0x00 0x4010c000 0x00 0x1000>;
  28. };
  29.  
  30. fccu@4030C000 {
  31. clock-names = "fccu";
  32. cfg_reg_val = <0x78 0x1540>;
  33. clocks = <0x04 0x30>;
  34. compatible = "fsl,s32gen1-fccu";
  35. status = "okay";
  36. cfg_reg_off = <0x98 0x54>;
  37. reg = <0x00 0x4030c000 0x00 0x3000>;
  38. };
  39.  
  40. mc_cgm1@40034000 {
  41. compatible = "fsl,s32gen1-mc_cgm1";
  42. reg = <0x00 0x40034000 0x00 0x3000>;
  43. };
  44.  
  45. crypto {
  46. #address-cells = <0x02>;
  47. #size-cells = <0x02>;
  48. compatible = "simple-bus";
  49. ranges = <0x00 0x00 0x00 0x40210000 0x00 0x4000>;
  50. #interrupt-cells = <0x03>;
  51.  
  52. mu0b@40210000 {
  53. interrupts = <0x00 0x67 0x01 0x00 0x68 0x01 0x00 0x69 0x01>;
  54. compatible = "fsl,s32gen1-hse";
  55. interrupt-names = "hse-mu0b-ack\0hse-mu0b-rx\0hse-mu0b-err";
  56. reg = <0x00 0x00 0x00 0x1000>;
  57. };
  58.  
  59. mu1b@40211000 {
  60. interrupts = <0x00 0x6a 0x01 0x00 0x6b 0x01 0x00 0x6c 0x01>;
  61. compatible = "fsl,s32gen1-hse";
  62. interrupt-names = "hse-mu1b-ack\0hse-mu1b-rx\0hse-mu1b-err";
  63. reg = <0x00 0x1000 0x00 0x1000>;
  64. };
  65.  
  66. mu2b@40212000 {
  67. interrupts = <0x00 0x6d 0x01 0x00 0x6e 0x01 0x00 0x6f 0x01>;
  68. compatible = "fsl,s32gen1-hse";
  69. interrupt-names = "hse-mu2b-ack\0hse-mu2b-rx\0hse-mu2b-err";
  70. reg = <0x00 0x2000 0x00 0x1000>;
  71. };
  72.  
  73. mu3b@40213000 {
  74. interrupts = <0x00 0x70 0x01 0x00 0x71 0x01 0x00 0x72 0x01>;
  75. compatible = "fsl,s32gen1-hse";
  76. interrupt-names = "hse-mu3b-ack\0hse-mu3b-rx\0hse-mu3b-err";
  77. reg = <0x00 0x3000 0x00 0x1000>;
  78. };
  79. };
  80.  
  81. i2c@402DC000 {
  82. #address-cells = <0x01>;
  83. clock-names = "ipg";
  84. interrupts = <0x00 0x60 0x04>;
  85. clocks = <0x04 0x30>;
  86. #size-cells = <0x00>;
  87. dma-names = "rx\0tx";
  88. compatible = "fsl,s32gen1-i2c";
  89. status = "okay";
  90. reg = <0x00 0x402dc000 0x00 0x1000>;
  91. dmas = <0x11 0x01 0x14 0x11 0x01 0x15>;
  92. };
  93.  
  94. spi@401DC000 {
  95. clock-names = "dspi";
  96. spi-num-chipselects = <0x05>;
  97. interrupts = <0x00 0x57 0x04>;
  98. clocks = <0x04 0x2c>;
  99. spi-cpol;
  100. compatible = "fsl,s32gen1-dspi";
  101. spi-extended-mode;
  102. status = "disabled";
  103. bus-num = <0x02>;
  104. spi-cpha;
  105. reg = <0x00 0x401dc000 0x00 0x3000>;
  106. spi-fifo-size = <0x05>;
  107. };
  108.  
  109. ethernet@46080000 {
  110. memory-region = <0x1b>;
  111. interrupts = <0x00 0xbe 0x01 0x00 0xbf 0x01 0x00 0xc0 0x01 0x00 0xc1 0x01 0x00 0xc2 0x01>;
  112. interrupt-parent = <0x01>;
  113. compatible = "fsl,s32g275-pfe";
  114. status = "okay";
  115. interrupt-names = "hif0\0hif1\0hif2\0hif3\0bmu";
  116. reg = <0x00 0x46000000 0x00 0x1000000>;
  117. };
  118.  
  119. i2c@402D8000 {
  120. #address-cells = <0x01>;
  121. clock-names = "ipg";
  122. interrupts = <0x00 0x5f 0x04>;
  123. clocks = <0x04 0x30>;
  124. #size-cells = <0x00>;
  125. dma-names = "rx\0tx";
  126. compatible = "fsl,s32gen1-i2c";
  127. status = "okay";
  128. reg = <0x00 0x402d8000 0x00 0x1000>;
  129. dmas = <0x11 0x01 0x12 0x11 0x01 0x13>;
  130. };
  131.  
  132. spi@401D8000 {
  133. pinctrl-names = "default";
  134. #address-cells = <0x01>;
  135. pinctrl-0 = <0x0f 0x10>;
  136. clock-names = "dspi";
  137. spi-num-chipselects = <0x05>;
  138. interrupts = <0x00 0x56 0x04>;
  139. clocks = <0x04 0x2c>;
  140. #size-cells = <0x00>;
  141. spi-cpol;
  142. compatible = "fsl,s32gen1-dspi";
  143. spi-extended-mode;
  144. status = "okay";
  145. bus-num = <0x01>;
  146. spi-cpha;
  147. reg = <0x00 0x401d8000 0x00 0x3000>;
  148. spi-fifo-size = <0x05>;
  149.  
  150. spidev@0 {
  151. spi-max-frequency = <0x3d0900>;
  152. compatible = "spidev";
  153. reg = <0x00>;
  154. };
  155. };
  156.  
  157. reset@40078000 {
  158. compatible = "fsl,s32gen1-reset";
  159. reg = <0x00 0x40078000 0x00 0x3000 0x00 0x40088000 0x00 0x1000>;
  160. };
  161.  
  162. clk10000000 {
  163. clock-output-names = "sysclk";
  164. #clock-cells = <0x00>;
  165. clock-frequency = <0x989680>;
  166. compatible = "fixed-clock";
  167. };
  168.  
  169. mc_cgm0@40030000 {
  170. compatible = "fsl,s32gen1-mc_cgm0";
  171. reg = <0x00 0x40030000 0x00 0x3000>;
  172. };
  173.  
  174. swt@40204000 {
  175. clock-names = "swt";
  176. clocks = <0x04 0x01>;
  177. compatible = "fsl,s32gen1-wdt";
  178. status = "okay";
  179. reg = <0x00 0x40204000 0x00 0x1000>;
  180. };
  181.  
  182. siul2_reg@0x44010000 {
  183. little-endian;
  184. compatible = "fsl,irq_reqs-s32gen1\0syscon\0simple-mfd";
  185. reg = <0x00 0x44010000 0x00 0x44>;
  186. phandle = <0x09>;
  187. };
  188.  
  189. pcie@40400000 {
  190. #address-cells = <0x03>;
  191. device_id = <0x00>;
  192. bus-range = <0x00 0xff>;
  193. reg-names = "dbi\0dbi2\0atu\0dma\0ctrl\0config\0addr_space";
  194. num-ob-windows = <0x06>;
  195. interrupts = <0x00 0x7c 0x04 0x00 0x7b 0x04 0x00 0x7d 0x04 0x00 0x7e 0x04 0x00 0x7f 0x04 0x00 0x84 0x04 0x00 0x85 0x04 0x00 0x86 0x04>;
  196. interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x80 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x81 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x82 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x83 0x04>;
  197. #size-cells = <0x02>;
  198. max-link-speed = <0x03>;
  199. device_type = "pci";
  200. interrupt-map-mask = <0x00 0x00 0x00 0x07>;
  201. num-lanes = <0x02>;
  202. compatible = "fsl,s32gen1-pcie";
  203. ranges = <0x81000000 0x00 0x00 0x58 0x3000 0x00 0x10000 0x82000000 0x00 0x13000 0x58 0x13000 0x00 0x40000000>;
  204. #interrupt-cells = <0x01>;
  205. status = "okay";
  206. interrupt-names = "link_req_stat\0dma\0msi\0phy_link_down\0phy_link_up\0misc\0pcs\0tlp_req_no_comp";
  207. reg = <0x00 0x40400000 0x00 0x1000 0x00 0x40420000 0x00 0x1000 0x00 0x40460000 0x00 0x1000 0x00 0x40470000 0x00 0x1000 0x00 0x40480000 0x00 0x4000 0x58 0x00 0x00 0x2000 0x58 0x40000000 0x00 0x40000000>;
  208. num-ib-windows = <0x06>;
  209. };
  210.  
  211. flexcan@402A8000 {
  212. pinctrl-names = "default";
  213. pinctrl-0 = <0x12 0x13>;
  214. clock-names = "per\0ipg";
  215. interrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04 0x00 0x30 0x04>;
  216. clocks = <0x04 0x35 0x04 0x30>;
  217. compatible = "fsl,s32gen1-flexcan";
  218. status = "okay";
  219. interrupt-names = "state\0berr\0mb_0-7\0mb_8-127";
  220. reg = <0x00 0x402a8000 0x00 0xa000>;
  221. };
  222.  
  223. rtc@40060000 {
  224. dividers = <0x01 0x00>;
  225. clksel = <0x02>;
  226. interrupts = <0x00 0x79 0x04>;
  227. compatible = "fsl,s32gen1-rtc";
  228. #interrupt-cells = <0x03>;
  229. reg = <0x00 0x40060000 0x00 0x1000>;
  230. };
  231.  
  232. clks@40038000 {
  233. #clock-cells = <0x01>;
  234. compatible = "fsl,s32g275-clocking";
  235. reg = <0x00 0x40038000 0x00 0x3000 0x00 0x4003c000 0x00 0x3000 0x00 0x40040000 0x00 0x3000 0x00 0x40044000 0x00 0x3000 0x00 0x40054000 0x00 0x3000 0x00 0x40058000 0x00 0x3000>;
  236. phandle = <0x04>;
  237. };
  238.  
  239. siul2_1 {
  240. #address-cells = <0x02>;
  241. midr-reg = <0x00 0x44010000 0x00 0x10>;
  242. #size-cells = <0x02>;
  243. compatible = "simple-mfd";
  244. ranges = <0x01 0x00 0x00 0x44010400 0x00 0x13c 0x02 0x00 0x00 0x44010c1c 0x00 0x5e4>;
  245. status = "okay";
  246.  
  247. siul2-gpio0@44010012 {
  248. regmap1 = <0x0c>;
  249. gpio-controller;
  250. interrupts = <0x00 0x10 0x04>;
  251. compatible = "fsl,s32gen1-siul2-gpio";
  252. regmap2 = <0x09>;
  253. status = "okay";
  254. regmap0 = <0x0b>;
  255. #gpio-cells = <0x02>;
  256. gpio-ranges = <0x08 0x00 0xb8 0x07 0x08 0x39e 0x39e 0x07>;
  257. interrupt-controller;
  258. };
  259.  
  260. siul2-gpio0@4401000E {
  261. regmap1 = <0x0c>;
  262. gpio-controller;
  263. interrupts = <0x00 0x0b 0x04>;
  264. compatible = "fsl,s32gen1-siul2-gpio";
  265. regmap2 = <0x09>;
  266. status = "okay";
  267. regmap0 = <0x0b>;
  268. #gpio-cells = <0x02>;
  269. gpio-ranges = <0x08 0x00 0xa8 0x01 0x08 0x399 0x399 0x01>;
  270. interrupt-controller;
  271. };
  272.  
  273. siul2-gpio0@44010002 {
  274. regmap1 = <0x0c>;
  275. gpio-controller;
  276. compatible = "fsl,s32gen1-siul2-gpio";
  277. status = "okay";
  278. regmap0 = <0x0b>;
  279. #gpio-cells = <0x02>;
  280. gpio-ranges = <0x08 0x00 0x70 0x01>;
  281. };
  282.  
  283. siul2-gpio0@44010010 {
  284. regmap1 = <0x0c>;
  285. gpio-controller;
  286. compatible = "fsl,s32gen1-siul2-gpio";
  287. status = "okay";
  288. regmap0 = <0x0b>;
  289. #gpio-cells = <0x02>;
  290. gpio-ranges = <0x08 0x00 0xa9 0x0f>;
  291. };
  292.  
  293. siul2-gpio0@4401000C {
  294. regmap1 = <0x0c>;
  295. gpio-controller;
  296. compatible = "fsl,s32gen1-siul2-gpio";
  297. status = "okay";
  298. regmap0 = <0x0b>;
  299. #gpio-cells = <0x02>;
  300. gpio-ranges = <0x08 0x00 0x90 0x18>;
  301. };
  302.  
  303. siul2-gpio0@4401000A {
  304. regmap1 = <0x0c>;
  305. gpio-controller;
  306. compatible = "fsl,s32gen1-siul2-gpio";
  307. status = "okay";
  308. regmap0 = <0x0b>;
  309. #gpio-cells = <0x02>;
  310. gpio-ranges = <0x08 0x00 0x76 0x05>;
  311. };
  312.  
  313. siul2-pinctrl1@44010000 {
  314. #pinctrl-cells = <0x02>;
  315. pins = <0x08 0x70 0xbe 0x08 0x277 0x3ef>;
  316. compatible = "fsl,s32g275-siul2_1-pinctrl";
  317. status = "okay";
  318. reg = <0x01 0x00 0x00 0x13c 0x02 0x00 0x00 0x5e4>;
  319. phandle = <0x08>;
  320.  
  321. s32g274a-evb {
  322.  
  323. dspi1grp {
  324. fsl,pins = <0x3db 0x02>;
  325. phandle = <0x10>;
  326. };
  327.  
  328. gpiogrp1 {
  329. fsl,pins = <0x70 0x00 0x92 0x00 0x93 0x00 0x94 0x00 0x95 0x00 0x96 0x00 0x97 0x00 0x98 0x00 0x99 0x00 0x9a 0x00 0x9b 0x00 0x9c 0x00 0x9d 0x00 0x9e 0x00 0x9f 0x00 0xa0 0x00 0xa1 0x00 0xa2 0x00 0xa3 0x00 0xa4 0x00 0xa5 0x00 0xa6 0x00 0xa7 0x00 0xa8 0x00 0xa9 0x00 0xaa 0x00 0xab 0x00 0xac 0x00 0xad 0x00 0xae 0x00 0xaf 0x00 0xb0 0x00 0xb1 0x00 0xb3 0x00 0xb4 0x00 0xb5 0x00 0xb6 0x00 0xb7 0x00 0xb8 0x00 0xb9 0x00 0xba 0x00 0xbb 0x00 0xbc 0x00 0xbd 0x00 0xbe 0x00>;
  330. };
  331.  
  332. can3grp {
  333. fsl,pins = <0x279 0x02>;
  334. phandle = <0x15>;
  335. };
  336.  
  337. rgmiiagrp {
  338. fsl,pins = <0x71 0x00 0x72 0x00 0x73 0x00 0x74 0x00 0x75 0x00 0x76 0x00 0x77 0x00 0x78 0x00 0x79 0x00 0x7a 0x00 0x90 0x00>;
  339. };
  340.  
  341. gpioeirqgrp0 {
  342. fsl,pins = <0x38e 0x02 0x38f 0x02 0x390 0x02 0x391 0x02 0x392 0x02 0x393 0x02 0x394 0x02 0x395 0x02 0x396 0x02 0x397 0x02 0x398 0x02 0x399 0x02 0x39a 0x02 0x39b 0x02 0x39c 0x02 0x39d 0x02 0x39e 0x02 0x39f 0x02 0x3a0 0x02 0x3a1 0x02 0x3a2 0x02 0x3a3 0x02 0x3a4 0x02 0x3a5 0x02 0x3a6 0x02 0x3a7 0x02 0x3a8 0x02 0x3a9 0x02 0x3aa 0x02 0x3ab 0x02 0x3ac 0x02 0x3ad 0x02>;
  343. phandle = <0x0a>;
  344. };
  345.  
  346. can2grp {
  347. fsl,pins = <0x278 0x02>;
  348. phandle = <0x13>;
  349. };
  350.  
  351. dspi5grp {
  352. fsl,pins = <0x3ef 0x02>;
  353. phandle = <0x17>;
  354. };
  355. };
  356. };
  357.  
  358. siul2-gpio0@44010008 {
  359. regmap1 = <0x0c>;
  360. gpio-controller;
  361. interrupts = <0x00 0x1a 0x04>;
  362. compatible = "fsl,s32gen1-siul2-gpio";
  363. regmap2 = <0x09>;
  364. status = "okay";
  365. regmap0 = <0x0b>;
  366. #gpio-cells = <0x02>;
  367. gpio-ranges = <0x08 0x00 0x75 0x01 0x08 0x3a8 0x3a8 0x01>;
  368. interrupt-controller;
  369. };
  370.  
  371. siul2-gpio0@44010006 {
  372. regmap1 = <0x0c>;
  373. gpio-controller;
  374. compatible = "fsl,s32gen1-siul2-gpio";
  375. status = "okay";
  376. regmap0 = <0x0b>;
  377. #gpio-cells = <0x02>;
  378. gpio-ranges = <0x08 0x00 0x74 0x01>;
  379. };
  380.  
  381. siul2-gpio0@44010004 {
  382. regmap1 = <0x0c>;
  383. gpio-controller;
  384. interrupts = <0x00 0x17 0x04>;
  385. compatible = "fsl,s32gen1-siul2-gpio";
  386. regmap2 = <0x09>;
  387. status = "okay";
  388. regmap0 = <0x0b>;
  389. #gpio-cells = <0x02>;
  390. gpio-ranges = <0x08 0x00 0x71 0x03 0x08 0x3a5 0x3a5 0x03>;
  391. interrupt-controller;
  392. };
  393. };
  394.  
  395. serial@402BC000 {
  396. clock-names = "lin\0ipg";
  397. interrupts = <0x00 0x54 0x01>;
  398. clocks = <0x04 0x2a 0x04 0x2b>;
  399. dma-names = "rx\0tx";
  400. compatible = "fsl,s32-linflexuart";
  401. reg = <0x00 0x402bc000 0x00 0x3000>;
  402. dmas = <0x11 0x01 0x04 0x11 0x01 0x03>;
  403. };
  404.  
  405. pit@40288000 {
  406. clock-names = "pit";
  407. interrupts = <0x00 0x36 0x04>;
  408. clocks = <0x04 0x30>;
  409. cpu = <0x01>;
  410. compatible = "fsl,s32gen1-pit";
  411. status = "okay";
  412. reg = <0x00 0x40288000 0x00 0x3000>;
  413. };
  414.  
  415. mc_cgm5@40068000 {
  416. compatible = "fsl,s32gen1-mc_cgm5";
  417. reg = <0x00 0x40068000 0x00 0x3000>;
  418. };
  419.  
  420. clocks {
  421. #address-cells = <0x01>;
  422. #size-cells = <0x00>;
  423.  
  424. firc {
  425. #clock-cells = <0x00>;
  426. clock-frequency = <0x2dc6c00>;
  427. compatible = "fixed-clock";
  428. };
  429.  
  430. fxosc {
  431. #clock-cells = <0x00>;
  432. clock-frequency = <0x2625a00>;
  433. compatible = "fixed-clock";
  434. };
  435.  
  436. sirc {
  437. #clock-cells = <0x00>;
  438. clock-frequency = <0x7d00>;
  439. compatible = "fixed-clock";
  440. };
  441. };
  442.  
  443. psci {
  444. method = "hvc";
  445. compatible = "arm,psci-1.0\0arm,psci-0.2\0arm,psci";
  446. cpu_on = <0x02>;
  447. cpu_off = <0x01>;
  448. };
  449.  
  450. hypervisor {
  451. interrupts = <0x01 0x00 0xf08>;
  452. interrupt-parent = <0x01>;
  453. compatible = "xen,xen-4.12\0xen,xen";
  454. reg = <0x00 0x80200000 0x00 0x40000>;
  455. };
  456.  
  457. mscm@40198000 {
  458. interrupts = <0x00 0x01 0x04 0x00 0x02 0x04 0x00 0x03 0x04>;
  459. compatible = "fsl,s32gen1-mscm";
  460. reg = <0x00 0x40198000 0x00 0x1000>;
  461. };
  462.  
  463. spi@401D4000 {
  464. clock-names = "dspi";
  465. spi-num-chipselects = <0x05>;
  466. interrupts = <0x00 0x55 0x04>;
  467. clocks = <0x04 0x2c>;
  468. spi-cpol;
  469. compatible = "fsl,s32gen1-dspi";
  470. spi-extended-mode;
  471. status = "disabled";
  472. bus-num = <0x00>;
  473. spi-cpha;
  474. reg = <0x00 0x401d4000 0x00 0x3000>;
  475. spi-fifo-size = <0x05>;
  476. };
  477.  
  478. pit@40188000 {
  479. clock-names = "pit";
  480. interrupts = <0x00 0x35 0x04>;
  481. clocks = <0x04 0x30>;
  482. cpu = <0x00>;
  483. compatible = "fsl,s32gen1-pit";
  484. status = "okay";
  485. reg = <0x00 0x40188000 0x00 0x3000>;
  486. };
  487.  
  488. i2c@401EC000 {
  489. #address-cells = <0x01>;
  490. clock-names = "ipg";
  491. interrupts = <0x00 0x5e 0x04>;
  492. clocks = <0x04 0x30>;
  493. #size-cells = <0x00>;
  494. dma-names = "rx\0tx";
  495. compatible = "fsl,s32gen1-i2c";
  496. status = "okay";
  497. reg = <0x00 0x401ec000 0x00 0x1000>;
  498. dmas = <0x11 0x01 0x10 0x11 0x01 0x11>;
  499. };
  500.  
  501. mc_cgm2@44018000 {
  502. compatible = "fsl,s32gen1-mc_cgm2";
  503. reg = <0x00 0x44018000 0x00 0x3000>;
  504. };
  505.  
  506. ethernet@4033c000 {
  507. pinctrl-names = "default";
  508. phy-mode = "rgmii";
  509. pinctrl-0 = <0x18 0x19>;
  510. clock-names = "stmmaceth\0pclk\0tx";
  511. interrupts = <0x00 0x39 0x04>;
  512. clocks = <0x04 0x2e 0x04 0x2e 0x04 0x38>;
  513. interrupt-parent = <0x01>;
  514. compatible = "fsl,s32cc-dwmac";
  515. status = "okay";
  516. tx-fifo-depth = <0x5000>;
  517. interrupt-names = "macirq";
  518. rx-fifo-depth = <0x5000>;
  519. reg = <0x00 0x4033c000 0x00 0x2000 0x00 0x4007c004 0x00 0x04>;
  520. phy-handle = <0x1a>;
  521.  
  522. mdio0 {
  523. #address-cells = <0x01>;
  524. #size-cells = <0x00>;
  525. compatible = "snps,dwmac-mdio";
  526.  
  527. ethernet-phy@5 {
  528. #address-cells = <0x01>;
  529. #size-cells = <0x00>;
  530. status = "disabled";
  531. reg = <0x05>;
  532. };
  533.  
  534. ethernet-phy@1 {
  535. #address-cells = <0x01>;
  536. #size-cells = <0x00>;
  537. compatible = "ethernet-phy-ieee802.3-c45";
  538. reg = <0x01>;
  539. };
  540.  
  541. ethernet-phy@4 {
  542. #address-cells = <0x01>;
  543. #size-cells = <0x00>;
  544. reg = <0x04>;
  545. phandle = <0x1a>;
  546. };
  547. };
  548. };
  549.  
  550. i2c@401E8000 {
  551. #address-cells = <0x01>;
  552. clock-names = "ipg";
  553. interrupts = <0x00 0x5d 0x04>;
  554. clocks = <0x04 0x30>;
  555. #size-cells = <0x00>;
  556. dma-names = "rx\0tx";
  557. compatible = "fsl,s32gen1-i2c";
  558. status = "okay";
  559. reg = <0x00 0x401e8000 0x00 0x1000>;
  560. dmas = <0x0e 0x00 0x12 0x0e 0x00 0x13>;
  561. };
  562.  
  563. usbmisc@44064200 {
  564. compatible = "fsl,s32g274a-usbmisc";
  565. #index-cells = <0x01>;
  566. reg = <0x00 0x44064200 0x00 0x200>;
  567. phandle = <0x1c>;
  568. };
  569.  
  570. flexcan@402B2000 {
  571. pinctrl-names = "default";
  572. pinctrl-0 = <0x14 0x15>;
  573. clock-names = "per\0ipg";
  574. interrupts = <0x00 0x31 0x04 0x00 0x32 0x04 0x00 0x33 0x04 0x00 0x34 0x04>;
  575. clocks = <0x04 0x35 0x04 0x30>;
  576. compatible = "fsl,s32gen1-flexcan";
  577. status = "okay";
  578. interrupt-names = "state\0berr\0mb_0-7\0mb_8-127";
  579. reg = <0x00 0x402b2000 0x00 0xa000>;
  580. };
  581.  
  582. swt@40200000 {
  583. clock-names = "swt";
  584. clocks = <0x04 0x01>;
  585. compatible = "fsl,s32gen1-wdt";
  586. status = "okay";
  587. reg = <0x00 0x40200000 0x00 0x1000>;
  588. };
  589.  
  590. usb@44064000 {
  591. tx-burst-size-dword = <0x10>;
  592. phy_type = "ulpi";
  593. interrupts = <0x00 0xd3 0x04 0x00 0xd4 0x04>;
  594. clocks = <0x04 0x31 0x04 0x02>;
  595. fsl,usbmisc = <0x1c 0x00>;
  596. interrupt-parent = <0x01>;
  597. rx-burst-size-dword = <0x10>;
  598. compatible = "fsl,s32g274a-usb";
  599. status = "disabled";
  600. reg = <0x00 0x44064000 0x00 0x200>;
  601. dr_mode = "host";
  602. maximum-speed = "high-speed";
  603. ahb-burst-config = <0x00>;
  604. };
  605.  
  606. timer {
  607. interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08>;
  608. interrupt-parent = <0x01>;
  609. clock-frequency = <0x4c4b40>;
  610. compatible = "arm,armv8-timer";
  611. };
  612.  
  613. a53_gpr@4007C400 {
  614. compatible = "fsl,s32gen1-a53gpr";
  615. reg = <0x00 0x4007c400 0x00 0x100>;
  616. };
  617.  
  618. stm@40120000 {
  619. clock-names = "stm";
  620. interrupts = <0x00 0x19 0x04>;
  621. clocks = <0x04 0x30>;
  622. cpu = <0x03>;
  623. compatible = "fsl,s32gen1-stm";
  624. status = "okay";
  625. reg = <0x00 0x40120000 0x00 0x3000>;
  626. };
  627.  
  628. siul2_reg@0x4401174C {
  629. big-endian;
  630. compatible = "fsl,ipad0_reqs-s32gen1\0syscon\0simple-mfd";
  631. reg = <0x00 0x4401174c 0x00 0x14>;
  632. phandle = <0x0c>;
  633. };
  634.  
  635. stm@4011C000 {
  636. clock-names = "stm";
  637. interrupts = <0x00 0x18 0x04>;
  638. clocks = <0x04 0x30>;
  639. cpu = <0x02>;
  640. compatible = "fsl,s32gen1-stm";
  641. status = "okay";
  642. reg = <0x00 0x4011c000 0x00 0x3000>;
  643. };
  644.  
  645. aliases {
  646. serial1 = "/serial@401CC000";
  647. can2 = "/flexcan@402A8000";
  648. can0 = "/flexcan@401B4000";
  649. serial2 = "/serial@402BC000";
  650. can3 = "/flexcan@402B2000";
  651. serial0 = "/serial@401C8000";
  652. can1 = "/flexcan@401BE000";
  653. };
  654.  
  655. spi@402D0000 {
  656. pinctrl-names = "default";
  657. #address-cells = <0x01>;
  658. pinctrl-0 = <0x16 0x17>;
  659. clock-names = "dspi";
  660. spi-num-chipselects = <0x05>;
  661. interrupts = <0x00 0x5a 0x04>;
  662. clocks = <0x04 0x2c>;
  663. #size-cells = <0x00>;
  664. spi-cpol;
  665. compatible = "fsl,s32gen1-dspi";
  666. spi-extended-mode;
  667. status = "okay";
  668. bus-num = <0x05>;
  669. spi-cpha;
  670. reg = <0x00 0x402d0000 0x00 0x3000>;
  671. spi-fifo-size = <0x05>;
  672.  
  673. sja1105p@0 {
  674. fsl,spi-sck-cs-delay = <0x64>;
  675. fsl,spi-cs-sck-delay = <0x64>;
  676. spi-max-frequency = <0x3d0900>;
  677. compatible = "nxp,sja1105p-switch";
  678. spi-cpha;
  679. reg = <0x00>;
  680.  
  681. port-3 {
  682. phy-ref = <0x00>;
  683. null-phy = <0x01>;
  684. is-host = <0x00>;
  685. };
  686.  
  687. port-1 {
  688. phy-ref = <0x00>;
  689. null-phy = <0x01>;
  690. is-host = <0x00>;
  691. };
  692.  
  693. port-4 {
  694. phy-ref = <0x00>;
  695. null-phy = <0x01>;
  696. is-host = <0x00>;
  697. };
  698.  
  699. port-2 {
  700. phy-ref = <0x00>;
  701. null-phy = <0x01>;
  702. is-host = <0x00>;
  703. };
  704.  
  705. port-0 {
  706. phy-ref = <0x00>;
  707. null-phy = <0x01>;
  708. is-host = <0x01>;
  709. };
  710. };
  711. };
  712.  
  713. spi@402CC000 {
  714. clock-names = "dspi";
  715. spi-num-chipselects = <0x05>;
  716. interrupts = <0x00 0x59 0x04>;
  717. clocks = <0x04 0x2c>;
  718. spi-cpol;
  719. compatible = "fsl,s32gen1-dspi";
  720. spi-extended-mode;
  721. status = "disabled";
  722. bus-num = <0x04>;
  723. spi-cpha;
  724. reg = <0x00 0x402cc000 0x00 0x3000>;
  725. spi-fifo-size = <0x05>;
  726. };
  727.  
  728. dma-controller@40244000 {
  729. clock-names = "dmamux0\0dmamux1";
  730. interrupts = <0x00 0x0b 0x04 0x00 0x0c 0x04 0x00 0x0d 0x04>;
  731. clocks = <0x04 0x2e 0x04 0x2e>;
  732. compatible = "fsl,s32gen1-edma";
  733. status = "okay";
  734. interrupt-names = "edma-tx_0-15\0edma-tx_16-31\0edma-err";
  735. reg = <0x00 0x40244000 0x00 0x24000 0x00 0x4022c000 0x00 0x3000 0x00 0x40230000 0x00 0x3000>;
  736. phandle = <0x11>;
  737. dma-channels = <0x20>;
  738. #dma-cells = <0x02>;
  739. };
  740.  
  741. spi@402C8000 {
  742. clock-names = "dspi";
  743. spi-num-chipselects = <0x05>;
  744. interrupts = <0x00 0x58 0x04>;
  745. clocks = <0x04 0x2c>;
  746. spi-cpol;
  747. compatible = "fsl,s32gen1-dspi";
  748. spi-extended-mode;
  749. status = "disabled";
  750. bus-num = <0x03>;
  751. spi-cpha;
  752. reg = <0x00 0x402c8000 0x00 0x3000>;
  753. spi-fifo-size = <0x05>;
  754. };
  755.  
  756. serial@401CC000 {
  757. clock-names = "lin\0ipg";
  758. interrupts = <0x00 0x53 0x01>;
  759. clocks = <0x04 0x2a 0x04 0x2b>;
  760. dma-names = "rx\0tx";
  761. compatible = "fsl,s32-linflexuart";
  762. reg = <0x00 0x401cc000 0x00 0x3000>;
  763. dmas = <0x0e 0x00 0x06 0x0e 0x00 0x05>;
  764. };
  765.  
  766. serial@401C8000 {
  767. clock-names = "lin\0ipg";
  768. interrupts = <0x00 0x52 0x01>;
  769. clocks = <0x04 0x2a 0x04 0x2b>;
  770. dma-names = "rx\0tx";
  771. compatible = "fsl,s32-linflexuart";
  772. reg = <0x00 0x401c8000 0x00 0x3000>;
  773. dmas = <0x0e 0x00 0x04 0x0e 0x00 0x03>;
  774. };
  775.  
  776. siul2_reg@0x4401170C {
  777. big-endian;
  778. compatible = "fsl,opad0_reqs-s32gen1\0syscon\0simple-mfd";
  779. reg = <0x00 0x4401170c 0x00 0x14>;
  780. phandle = <0x0b>;
  781. };
  782.  
  783. chosen {
  784. #address-cells = <0x01>;
  785. bootargs = "console=ttyLF0,115200 root=/dev/mmcblk0p2 rootwait rw";
  786. #size-cells = <0x01>;
  787. };
  788.  
  789. virtio_block@39501000 {
  790. interrupts = <0x00 0x44 0x04>;
  791. compatible = "virtio,mmio";
  792. reg = <0x00 0x39501000 0x00 0x1000>;
  793. };
  794.  
  795. pcie@44100000 {
  796. #address-cells = <0x03>;
  797. device_id = <0x01>;
  798. bus-range = <0x00 0xff>;
  799. reg-names = "dbi\0dbi2\0atu\0dma\0ctrl\0config\0addr_space";
  800. num-ob-windows = <0x06>;
  801. interrupts = <0x00 0xd7 0x04 0x00 0xd6 0x04 0x00 0xd8 0x04 0x00 0xd9 0x04 0x00 0xda 0x04 0x00 0xdf 0x04 0x00 0xe0 0x04 0x00 0xe1 0x04>;
  802. interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0xdb 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0xdc 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0xdd 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0xde 0x04>;
  803. #size-cells = <0x02>;
  804. max-link-speed = <0x03>;
  805. device_type = "pci";
  806. interrupt-map-mask = <0x00 0x00 0x00 0x07>;
  807. num-lanes = <0x01>;
  808. compatible = "fsl,s32gen1-pcie";
  809. ranges = <0x81000000 0x00 0x00 0x48 0x3000 0x00 0x10000 0x82000000 0x00 0x13000 0x48 0x13000 0x00 0x40000000>;
  810. #interrupt-cells = <0x01>;
  811. status = "okay";
  812. interrupt-names = "link_req_stat\0dma\0msi\0phy_link_down\0phy_link_up\0misc\0pcs\0tlp_req_no_comp";
  813. reg = <0x00 0x44100000 0x00 0x1000 0x00 0x44120000 0x00 0x1000 0x00 0x44160000 0x00 0x1000 0x00 0x44170000 0x00 0x1000 0x00 0x44180000 0x00 0x4000 0x48 0x00 0x00 0x2000 0x48 0x40000000 0x00 0x40000000>;
  814. num-ib-windows = <0x06>;
  815. };
  816.  
  817. dma-controller@40144000 {
  818. clock-names = "dmamux0\0dmamux1";
  819. interrupts = <0x00 0x08 0x04 0x00 0x09 0x04 0x00 0x0a 0x04>;
  820. clocks = <0x04 0x2e 0x04 0x2e>;
  821. compatible = "fsl,s32gen1-edma";
  822. status = "okay";
  823. interrupt-names = "edma-tx_0-15\0edma-tx_16-31\0edma-err";
  824. reg = <0x00 0x40144000 0x00 0x24000 0x00 0x4012c000 0x00 0x3000 0x00 0x40130000 0x00 0x3000>;
  825. phandle = <0x0e>;
  826. dma-channels = <0x20>;
  827. #dma-cells = <0x02>;
  828. };
  829.  
  830. swt@40208000 {
  831. clock-names = "swt";
  832. clocks = <0x04 0x01>;
  833. compatible = "fsl,s32gen1-wdt";
  834. status = "okay";
  835. reg = <0x00 0x40208000 0x00 0x1000>;
  836. };
  837.  
  838. siul2_0 {
  839. #address-cells = <0x02>;
  840. midr-reg = <0x00 0x4009c000 0x00 0x10>;
  841. #size-cells = <0x02>;
  842. compatible = "simple-mfd";
  843. ranges = <0x01 0x00 0x00 0x4009c240 0x00 0x198 0x02 0x00 0x00 0x4009ca40 0x00 0x150>;
  844. status = "okay";
  845.  
  846. siul2-gpio0@4009C008 {
  847. pinctrl-names = "default";
  848. regmap1 = <0x07>;
  849. gpio-controller;
  850. interrupts = <0x00 0x0c 0x04>;
  851. compatible = "fsl,s32gen1-siul2-gpio";
  852. regmap2 = <0x09>;
  853. status = "okay";
  854. regmap0 = <0x06>;
  855. #gpio-cells = <0x02>;
  856. gpio-ranges = <0x05 0x00 0x1f 0x01 0x08 0x39a 0x39a 0x01>;
  857. interrupt-controller;
  858. };
  859.  
  860. siul2-gpio0@4009C006 {
  861. regmap1 = <0x07>;
  862. gpio-controller;
  863. compatible = "fsl,s32gen1-siul2-gpio";
  864. status = "okay";
  865. regmap0 = <0x06>;
  866. #gpio-cells = <0x02>;
  867. gpio-ranges = <0x05 0x00 0x1e 0x01>;
  868. };
  869.  
  870. siul2-gpio0@4009C004 {
  871. pinctrl-names = "default";
  872. regmap1 = <0x07>;
  873. pinctrl-0 = <0x0a>;
  874. gpio-controller;
  875. interrupts = <0x00 0x00 0x04>;
  876. compatible = "fsl,s32gen1-siul2-gpio";
  877. regmap2 = <0x09>;
  878. status = "okay";
  879. regmap0 = <0x06>;
  880. #gpio-cells = <0x02>;
  881. gpio-ranges = <0x05 0x00 0x13 0x0b 0x08 0x38e 0x38e 0x0b>;
  882. interrupt-controller;
  883. };
  884.  
  885. siul2-gpio0@4009C00E {
  886. pinctrl-names = "default";
  887. regmap1 = <0x07>;
  888. gpio-controller;
  889. interrupts = <0x00 0x1b 0x04>;
  890. compatible = "fsl,s32gen1-siul2-gpio";
  891. regmap2 = <0x09>;
  892. status = "okay";
  893. regmap0 = <0x06>;
  894. #gpio-cells = <0x02>;
  895. gpio-ranges = <0x05 0x00 0x24 0x05 0x08 0x3a9 0x3a9 0x05>;
  896. interrupt-controller;
  897. };
  898.  
  899. siul2-gpio0@4009C002 {
  900. regmap1 = <0x07>;
  901. gpio-controller;
  902. compatible = "fsl,s32gen1-siul2-gpio";
  903. status = "okay";
  904. regmap0 = <0x06>;
  905. #gpio-cells = <0x02>;
  906. gpio-ranges = <0x05 0x00 0x00 0x13>;
  907. };
  908.  
  909. siul2-gpio0@4009C010 {
  910. regmap1 = <0x07>;
  911. gpio-controller;
  912. compatible = "fsl,s32gen1-siul2-gpio";
  913. status = "okay";
  914. regmap0 = <0x06>;
  915. #gpio-cells = <0x02>;
  916. gpio-ranges = <0x05 0x00 0x29 0x3d>;
  917. };
  918.  
  919. siul2-gpio0@4009C00C {
  920. pinctrl-names = "default";
  921. regmap1 = <0x07>;
  922. gpio-controller;
  923. interrupts = <0x00 0x0d 0x04>;
  924. compatible = "fsl,s32gen1-siul2-gpio";
  925. regmap2 = <0x09>;
  926. status = "okay";
  927. regmap0 = <0x06>;
  928. #gpio-cells = <0x02>;
  929. gpio-ranges = <0x05 0x00 0x21 0x03 0x08 0x39b 0x39b 0x03>;
  930. interrupt-controller;
  931. };
  932.  
  933. siul2-gpio0@4009C00A {
  934. regmap1 = <0x07>;
  935. gpio-controller;
  936. compatible = "fsl,s32gen1-siul2-gpio";
  937. status = "okay";
  938. regmap0 = <0x06>;
  939. #gpio-cells = <0x02>;
  940. gpio-ranges = <0x05 0x00 0x20 0x01>;
  941. };
  942.  
  943. siul2-pinctrl0@4009C000 {
  944. #pinctrl-cells = <0x02>;
  945. pins = <0x05 0x00 0x65 0x05 0x200 0x253>;
  946. compatible = "fsl,s32g275-siul2_0-pinctrl";
  947. status = "okay";
  948. reg = <0x01 0x00 0x00 0x198 0x02 0x00 0x00 0x150>;
  949. phandle = <0x05>;
  950.  
  951. s32g274a-evb {
  952.  
  953. mdiocgrp {
  954. fsl,pins = <0x3c 0x200001 0x3d 0x280001 0x20f 0x02>;
  955. phandle = <0x19>;
  956. };
  957.  
  958. dspi1grp {
  959. fsl,pins = <0x07 0x203002 0x06 0x200002 0x08 0x200003 0x5f 0x83000>;
  960. phandle = <0x0f>;
  961. };
  962.  
  963. can3grp {
  964. fsl,pins = <0x19 0x214002 0x1a 0x80000>;
  965. phandle = <0x14>;
  966. };
  967.  
  968. can0grp {
  969. fsl,pins = <0x2c 0x214001 0x2b 0x80000 0x201 0x02>;
  970. phandle = <0x0d>;
  971. };
  972.  
  973. rgmiiagrp {
  974. fsl,pins = <0x4e 0x00>;
  975. };
  976.  
  977. can2grp {
  978. fsl,pins = <0x1b 0x214002 0x1c 0x80000>;
  979. phandle = <0x12>;
  980. };
  981.  
  982. gpiogrp0 {
  983. fsl,pins = <0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x00 0x04 0x00 0x05 0x00 0x06 0x00 0x07 0x00 0x08 0x00 0x09 0x00 0x0a 0x00 0x0b 0x00 0x0c 0x00 0x0d 0x00 0x0e 0x00 0x0f 0x00 0x10 0x00 0x11 0x00 0x12 0x00 0x13 0x00 0x14 0x00 0x15 0x00 0x16 0x00 0x17 0x00 0x18 0x00 0x19 0x00 0x1a 0x00 0x1b 0x00 0x1c 0x00 0x1d 0x00 0x1e 0x00 0x1f 0x00 0x20 0x00 0x21 0x00 0x22 0x00 0x23 0x00 0x24 0x00 0x25 0x00 0x26 0x00 0x27 0x00 0x28 0x00 0x29 0x00 0x2a 0x00 0x2b 0x00 0x2c 0x00 0x2d 0x00 0x2e 0x00 0x2f 0x00 0x30 0x00 0x31 0x00 0x32 0x00 0x33 0x00 0x34 0x00 0x35 0x00 0x36 0x00 0x37 0x00 0x38 0x00 0x39 0x00 0x3a 0x00 0x3b 0x00 0x3c 0x00 0x3d 0x00 0x3e 0x00 0x3f 0x00 0x40 0x00 0x41 0x00 0x42 0x00 0x43 0x00 0x44 0x00 0x45 0x00 0x46 0x00 0x47 0x00 0x48 0x00 0x49 0x00 0x4a 0x00 0x4b 0x00 0x4c 0x00 0x4d 0x00 0x4e 0x00 0x4f 0x00 0x50 0x00 0x51 0x00 0x52 0x00 0x53 0x00 0x54 0x00 0x55 0x00 0x56 0x00 0x57 0x00 0x58 0x00 0x59 0x00 0x5a 0x00 0x5b 0x00 0x5c 0x00 0x5d 0x00 0x5e 0x00 0x5f 0x00 0x60 0x00 0x61 0x00 0x62 0x00 0x63 0x00 0x64 0x00 0x65 0x00>;
  984. };
  985.  
  986. dspi5grp {
  987. fsl,pins = <0x0c 0x203003 0x0b 0x200003 0x09 0x200003 0x0a 0x83000>;
  988. phandle = <0x16>;
  989. };
  990.  
  991. mdioagrp {
  992. fsl,pins = <0x4f 0x00 0x52 0x00>;
  993. };
  994.  
  995. rgmiicgrp {
  996. fsl,pins = <0x42 0x203001 0x21a 0x02 0x43 0x200001 0x44 0x200001 0x45 0x200001 0x46 0x200001 0x47 0x200001 0x48 0x80000 0x211 0x02 0x49 0x80000 0x212 0x02 0x4a 0x80000 0x213 0x02 0x4b 0x80000 0x214 0x02 0x4c 0x80000 0x215 0x02 0x4d 0x80000 0x216 0x02>;
  997. phandle = <0x18>;
  998. };
  999. };
  1000. };
  1001. };
  1002.  
  1003. cpus {
  1004. #address-cells = <0x01>;
  1005. #size-cells = <0x00>;
  1006.  
  1007. cpu@1 {
  1008. device_type = "cpu";
  1009. compatible = "arm,cortex-a53";
  1010. reg = <0x01>;
  1011. enable-method = "psci";
  1012. };
  1013.  
  1014. cpu@2 {
  1015. device_type = "cpu";
  1016. compatible = "arm,cortex-a53";
  1017. reg = <0x02>;
  1018. enable-method = "psci";
  1019. };
  1020.  
  1021. cpu@0 {
  1022. device_type = "cpu";
  1023. compatible = "arm,cortex-a53";
  1024. reg = <0x00>;
  1025. enable-method = "psci";
  1026. };
  1027.  
  1028. cpu@3 {
  1029. device_type = "cpu";
  1030. compatible = "arm,cortex-a53";
  1031. reg = <0x03>;
  1032. enable-method = "psci";
  1033. };
  1034. };
  1035.  
  1036. i2c@401E4000 {
  1037. #address-cells = <0x01>;
  1038. clock-names = "ipg";
  1039. interrupts = <0x00 0x5c 0x04>;
  1040. clocks = <0x04 0x30>;
  1041. #size-cells = <0x00>;
  1042. dma-names = "rx\0tx";
  1043. compatible = "fsl,s32gen1-i2c";
  1044. status = "okay";
  1045. reg = <0x00 0x401e4000 0x00 0x1000>;
  1046. dmas = <0x0e 0x00 0x10 0x0e 0x00 0x11>;
  1047. };
  1048.  
  1049. siul2_reg@0x4009D740 {
  1050. big-endian;
  1051. compatible = "fsl,ipad0_reqs-s32gen1\0syscon\0simple-mfd";
  1052. reg = <0x00 0x4009d740 0x00 0x10>;
  1053. phandle = <0x07>;
  1054. };
  1055.  
  1056. usdhc@402F0000 {
  1057. clock-names = "ipg\0ahb\0per";
  1058. bus-width = <0x08>;
  1059. interrupts = <0x00 0x24 0x04>;
  1060. clocks = <0x04 0x30 0x04 0x2e 0x04 0x34>;
  1061. compatible = "fsl,s32gen1-usdhc";
  1062. status = "okay";
  1063. reg = <0x00 0x402f0000 0x00 0x1000>;
  1064. };
  1065.  
  1066. reserved-memory {
  1067. #address-cells = <0x02>;
  1068. #size-cells = <0x02>;
  1069. ranges;
  1070.  
  1071. shm@0xc0000000 {
  1072. compatible = "fsl,s32gen1-shm";
  1073. reg = <0x00 0xc0000000 0x00 0x400000>;
  1074. no-map;
  1075. };
  1076.  
  1077. pfebufs@83400000 {
  1078. compatible = "fsl,s32g-pfe-ddr";
  1079. status = "okay";
  1080. reg = <0x00 0x83400000 0x00 0xc00000>;
  1081. phandle = <0x1b>;
  1082. no-map;
  1083. };
  1084. };
  1085.  
  1086. flexcan@401BE000 {
  1087. clock-names = "per\0ipg";
  1088. interrupts = <0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04>;
  1089. clocks = <0x04 0x35 0x04 0x30>;
  1090. compatible = "fsl,s32gen1-flexcan";
  1091. status = "disabled";
  1092. interrupt-names = "state\0berr\0mb_0-7\0mb_8-127";
  1093. reg = <0x00 0x401be000 0x00 0xa000>;
  1094. };
  1095.  
  1096. interrupt-controller {
  1097. #address-cells = <0x02>;
  1098. #redistributor-regions = <0x01>;
  1099. #size-cells = <0x02>;
  1100. compatible = "arm,gic-v3";
  1101. #interrupt-cells = <0x03>;
  1102. reg = <0x00 0x50800000 0x00 0x10000 0x00 0x50880000 0x00 0x200000>;
  1103. phandle = <0x01>;
  1104. interrupt-controller;
  1105. };
  1106.  
  1107. memory {
  1108. device_type = "memory";
  1109. reg = <0x00 0x84000000 0x00 0x18000000>;
  1110. };
  1111.  
  1112. siul2_reg@0x4009D700 {
  1113. big-endian;
  1114. compatible = "fsl,opad0_reqs-s32gen1\0syscon\0simple-mfd";
  1115. reg = <0x00 0x4009d700 0x00 0x10>;
  1116. phandle = <0x06>;
  1117. };
  1118. };
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