Inversor CMOS

.SUBCKT NOT_GATE IN VDD VSS OUT

MN OUT IN VSS VSS NMOS1 w=1u l=1u
.MODEL NMOS1 NMOS VT0=1.5

MP OUT IN VDD VDD PMOS1 w=1u l=1u
.MODEL PMOS1 PMOS VT0=-1.5

.ENDS


X1 IN VDD 0 OUT NOT_GATE
C1 OUT 0 15p
VDD VDD 0 5
VIN IN 0 DC 5 PULSE (0 5 0 1e-9 1e-9 1e-4 2e-4)