API tools faq
paste
Advertisement
Guest User

Untitled

a guest
Jun 28th, 2017
89
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 21.60 KB | None | 0 0
raw download clone embed print report
  1. #ifndef _SIM_H_
  2. #define _SIM_H_
  3.  
  4.  
  5. #include <stdint.h>
  6. #include <math.h>
  7. #include <stdio.h>
  8. #include <stdlib.h>
  9.  
  10. struct cache{
  11. uint32_t assoc; /* associatividade, 1 para map. direto */
  12. uint32_t block; /* número de bytes por bloco */
  13. uint32_t num_blocks; /* número de blocos por conjunto */
  14. uint32_t lat; /* latência de acesso em ciclos */
  15. };
  16.  
  17.  
  18. struct stats{
  19. unsigned long *hits; /* vetor para cada nível de cache */
  20. unsigned long *misses; /* idem */
  21. unsigned long cycles; /* número total de ciclos da simulação */
  22. };
  23.  
  24. /** Recebe um traço de endereços de memória acessados e simula hierarquia de memória
  25. * @param configs vetor de configurações de caches
  26. * @param num_configs número de níveis de cache
  27. * @param mem_lat latência em ciclos de acesso à memória
  28. * @param filename nome do arquivo de traço (ou null)
  29. * @param stream stream com traço (se filename for null)
  30. * @return estatísticas de simulação
  31. */
  32. struct stats * sim(struct cache * configs, int num_configs,
  33. uint32_t mem_lat, char * filename, char * stream);
  34.  
  35. void setValues(uint32_t* tag, uint32_t* index, uint32_t size,struct cache * configs);
  36. void getValues(uint32_t*tag,uint32_t*index,uint32_t tagsize,uint32_t indexsize, uint32_t end);
  37. int _hash(char * str, int num_blocks, int assoc);
  38. int cacheSize(int assoc, int num_blocks, int block);
  39. void startStats(struct stats * sim);
  40. void LRUstart(uint32_t * Cache, uint32_t size);
  41. int dirMapped(uint32_t * Cache, int tag, int pos, int cycles,char mode,int extra);
  42. int assocMapped(uint32_t * Cache, int tag, int pos, int cycles, char mode,int extra, struct cache * configs);
  43. int getBlockPos(int index,int num_blocks);
  44. int acessCache(struct cache * configs,struct stats * sim,uint32_t * Cache, uint32_t end,int num_configs, uint32_t mem_lat,char mode);
  45. int fullyAssoc(uint32_t * Cache, int tag,int pos, int cycles, char mode,int extra,int num_blocks);
  46.  
  47. uint32_t hex2int(char *hex);
  48.  
  49.  
  50. /* TAG - BLOCK INDEX - OFFSET */
  51.  
  52. int main(){
  53. //testa so mem
  54. /*
  55. char * trace = "R 12345678\nW 90ABCDEF\n";
  56. struct stats * res = sim(NULL, 0, 10, NULL, trace);
  57. */
  58. //testa l1
  59. //char * trace = "R 12345678\nW 90ABCDEF\n";
  60. // struct cache mycache = {1, 4, 2, 1};
  61. // struct stats * res = sim(&mycache, 1, 10, NULL, NULL);
  62.  
  63. /*char * filename = "filename";
  64. char * trace = "R 12345678\nR 12345678\n";
  65. struct stats * res = sim(&mycache, 1, 10, NULL, trace);
  66. */
  67. struct cache mycache2 = {2, 8, 4, 1};
  68. char * trace3 = "R 12345678\nW 90ABCDEF\nW 00000410\nW 00000324\nW 000003ec\nW 00000410\n";
  69. struct stats * res = sim(&mycache2, 1, 10, NULL, NULL);
  70. return 0;
  71. }
  72.  
  73. struct stats * sim(struct cache * configs, int num_configs, uint32_t mem_lat, char * filename, char * stream){
  74. struct stats *sim = malloc(sizeof(struct stats));
  75. FILE *fp = fopen("C:\\Users\\Laster\\Documents\\Standard\\Estudos\\filename.txt","r");
  76. int size = 0;
  77. uint32_t end, i = 0,indexsize, tagsize;
  78. char *p = stream, str[11];
  79. struct cache * q;
  80. printf("test\n");
  81. printf("test\n");
  82. printf("test\n");
  83. if(configs != NULL){
  84. size = cacheSize(configs->assoc,configs->num_blocks,configs->block);
  85. setValues(&tagsize,&indexsize,size, configs);
  86. }
  87.  
  88. startStats(sim);
  89. uint32_t Cache[configs->num_blocks];
  90. uint32_t * Cache2;
  91. if(num_configs == 0){ //ACESSO DIRETO A MEMORIA
  92. (*sim).cycles += mem_lat;
  93. return sim;
  94. }
  95. if(num_configs == 2){
  96. q = configs++;
  97. // uint32_t Cache2[q->num_blocks];
  98. Cache2 = malloc(sizeof(uint32_t)*(q->num_blocks));
  99. }
  100.  
  101. if(fp != NULL) // TEM ARQUIVO
  102. {
  103. while(fscanf(fp,"%[^\n]\n",str) != EOF)
  104. {
  105. end = hex2int(str);
  106. if(num_configs == 2){
  107. if(acessCache(configs,sim,Cache,end,num_configs,mem_lat,str[0])){ //hit na l1: update LRU and leave
  108. sim->cycles += configs->lat;
  109. *(*sim).hits += 1;
  110. }
  111. else{
  112. if(acessCache(q,sim,Cache2,end,num_configs,mem_lat,str[0])) //hit na l2: updates l2 LRU and bring it to l1
  113. {
  114. sim->cycles += q->lat;
  115. *(*sim).hits += 1;
  116. }
  117. else{
  118. sim->cycles += configs->lat;
  119. (*sim).cycles += mem_lat;
  120. *(*sim).misses += 1;
  121. }
  122. }
  123. }
  124. else{
  125. if(acessCache(configs,sim,Cache,end,num_configs,mem_lat,str[0])){ //hit
  126. sim->cycles += configs->lat;
  127. *(*sim).hits += 1;
  128. }
  129. else{//miss
  130. (*sim).cycles += 1;
  131. (*sim).cycles += mem_lat;
  132. *(*sim).misses += 1;
  133. }
  134. }
  135. }
  136. return sim;
  137. }
  138. else // USAR STREAM
  139. {
  140. while( *p != '\0'){
  141. while(*p != '\n' && *p != '\0'){ //pega o endereço em string
  142. str[i] = *p;
  143. i++;p++;
  144. }
  145. p++; i = 0;
  146. str[i] = '\0';
  147. end = hex2int(str);
  148.  
  149.  
  150.  
  151. //getValues(&tag,&index,tagsize,indexsize,end);
  152. if(num_configs == 2){
  153. if(acessCache(configs,sim,Cache,end,num_configs,mem_lat,str[0])){ //hit na l1: update LRU and leave
  154. sim->cycles += configs->lat;
  155. *(*sim).hits += 1;
  156. }
  157. else{
  158. if(acessCache(q,sim,Cache2,end,num_configs,mem_lat,str[0])) //hit na l2: updates l2 LRU and bring it to l1
  159. {
  160. sim->cycles += q->lat;
  161. *(*sim).hits += 1;
  162. }
  163. else{
  164. sim->cycles += configs->lat;
  165. (*sim).cycles += mem_lat;
  166. *(*sim).misses += 1;
  167. }
  168. }
  169. }
  170. else{
  171. if(acessCache(configs,sim,Cache,end,num_configs,mem_lat,str[0])){ //hit
  172. sim->cycles += configs->lat;
  173. *(*sim).hits += 1;
  174. }
  175. else{//miss
  176. (*sim).cycles += 1;
  177. (*sim).cycles += mem_lat;
  178. *(*sim).misses += 1;
  179. }
  180. }
  181. /*
  182. if(num_configs == 0){ //ACESSO DIRETO A MEMORIA
  183. (*sim).cycles += mem_lat;
  184. }
  185. else if(num_configs == 1){ //ACESSO L1
  186. //end = _hash(str1,configs->num_blocks,configs->assoc);
  187.  
  188. pos = getBlockPos(index,configs->num_blocks);
  189. printf("\npos=%d\n", pos);
  190. if(configs->assoc == 1){ //mapeando direto
  191. if(dirMapped(Cache,tag,pos,sim->cycles,str[0],extra)){ //hit
  192. sim->cycles += configs->lat;
  193. *(*sim).hits += 1;
  194. }
  195. else{//miss
  196. if(extra == 1){(*sim).cycles += mem_lat;} //if it was a miss in a writtenblock then writeback policy
  197. (*sim).cycles += 1;
  198. (*sim).cycles += mem_lat;
  199. *(*sim).misses += 1;
  200. }
  201. extra = 0;
  202. }
  203. else if(configs->assoc == configs->num_blocks){ //assoaciatividade completa
  204.  
  205. }
  206. else{ //associativo
  207. if(assocMapped(Cache,tag,pos,sim->cycles,str[0],extra,configs)){
  208. sim->cycles += configs->lat;
  209. *(*sim).hits += 1;
  210. }
  211. else{//miss
  212. if(extra == 1){(*sim).cycles += mem_lat;} //if it was a miss in a writtenblock then writeback policy
  213. (*sim).cycles += 1;
  214. (*sim).cycles += mem_lat;
  215. *(*sim).misses += 1;
  216. }
  217. }
  218. }
  219. else{ //ACESSO l2
  220.  
  221. }*/
  222. }
  223. }
  224. return sim;
  225. }
  226.  
  227. /*void push2l1(struct cache * configs,struct stats * sim,uint32_t * Cache,int pos, int cycles, char mode){
  228. aux = tag; aux <<= 10;
  229. timer = cycles;
  230. aux = aux | timer;
  231. if(configs->assoc == 1){ //mapeando direto, só 1 posição possivel
  232. if(mode == 'R'){
  233. Cache[pos] = 1;
  234. Cache[pos] = Cache[pos] << 31;
  235. }
  236. else{
  237. Cache[pos] = 3;
  238. Cache[pos] = Cache[pos] << 30;
  239. }
  240. }
  241. else if(configs->assoc == configs->num_blocks){ //fully associative
  242. }
  243. else{ //associativo
  244. }
  245. }*/
  246. int assocMapped(uint32_t * Cache, int tag, int pos, int cycles, char mode,int extra, struct cache * configs){
  247. uint32_t tTag, timer = cycles, V, D, aux, i, LRUpos = cycles;
  248. for(i=0;i<configs->assoc;i++){ //laço para encontrar um bloco vazio
  249. V = Cache[pos] >> 31;
  250. D = Cache[pos] << 1 >> 31;
  251. aux = tag; aux <<= 10;
  252. timer = cycles;
  253. aux = aux | timer; //aux OR timer, coloca tag e timer da LRU nos bits
  254.  
  255. if(V == 0){ //checks if its not inicialized, else verifies if its a hit
  256. V = 1;
  257. if(mode == 'R'){
  258. Cache[pos] = 1;
  259. Cache[pos] = Cache[pos] << 31;
  260. }
  261. else{
  262. Cache[pos] = 3;
  263. Cache[pos] = Cache[pos] << 30;
  264. }
  265.  
  266. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  267. printf("%d", Cache[pos]);
  268. return 0; //return miss
  269. }
  270. else{
  271. tTag = Cache[pos] << 2; tTag = tTag >> 12;
  272. if(tag == tTag){ // HIT
  273. if(mode == 'R'){
  274. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  275. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  276. }
  277. else{
  278. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  279. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  280. }
  281. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  282. Cache[pos] = Cache[pos] << 10;
  283. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  284. return 1; //return hit
  285. }
  286. if((Cache[pos] << 22 >> 22) < timer){ //finds the least recently used block in case theres no free block
  287. LRUpos = pos;
  288. }
  289. }
  290. pos += configs->num_blocks;
  291. }
  292. //at this point theres no empty block, and no hits, so we use LRU policy
  293. pos = LRUpos;
  294. D = Cache[pos] << 1 >> 31;
  295. V = Cache[pos] >> 31;
  296. aux = tag; aux <<= 10;
  297. timer = cycles;
  298. aux = aux | timer; //aux OR timer, coloca tag e timer da LRU nos bits
  299.  
  300. if(D == 1){ extra = 1; }
  301. if(mode == 'R'){
  302. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  303. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  304. }
  305. else{
  306. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  307. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  308. }
  309. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  310. Cache[pos] = Cache[pos] << 10;
  311. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  312. return 0;
  313. }
  314. int dirMapped(uint32_t * Cache, int tag, int pos, int cycles, char mode,int extra){
  315. uint32_t tTag, timer, V, D, aux;
  316. D = Cache[pos] << 1 >> 31;
  317. V = Cache[pos] >> 31;
  318. aux = tag; aux <<= 10;
  319. timer = cycles;
  320. aux = aux | timer; //aux OR timer, coloca tag e timer da LRU nos bits
  321.  
  322. if(V == 0){ //bloco nao utilizado antes, logo miss
  323. V = 1;
  324. if(mode == 'R')
  325. Cache[pos] = 1; //Cache[pos] = Cache[pos] << 30;
  326. else
  327. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  328. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  329. return 0; //return miss
  330. }
  331. else{ //
  332. timer = Cache[pos] << 22; timer = timer >> 22;
  333. tTag = Cache[pos] << 2; tTag = tTag >> 12;
  334. if(tag == tTag){ // HIT
  335. if(mode == 'R'){
  336. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  337. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  338. }
  339. else{
  340. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  341. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  342. }
  343. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  344. Cache[pos] = Cache[pos] << 10;
  345. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  346. return 1; //return hit
  347. }
  348. else{ //MISS
  349. if(D == 1){ extra = 1; }
  350. if(mode == 'R'){
  351. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  352. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  353. }
  354. else{
  355. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  356. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  357. }
  358. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  359. Cache[pos] = Cache[pos] << 10;
  360. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  361. }
  362. }
  363. return 0;
  364. }
  365.  
  366. int fullyAssoc(uint32_t * Cache, int tag,int pos, int cycles, char mode,int extra,int num_blocks){
  367. uint32_t tTag, timer = cycles, V, D, aux, LRUpos = cycles;
  368. for(pos=0;pos<num_blocks;pos++){ //laço para encontrar um bloco vazio
  369. V = Cache[pos] >> 31;
  370. D = Cache[pos] << 1 >> 31;
  371. aux = tag; aux <<= 10;
  372. timer = cycles;
  373. aux = aux | timer; //aux OR timer, coloca tag e timer da LRU nos bits
  374.  
  375. if(V == 0){ //checks if its not initialized, else verifies if its a hit
  376. V = 1;
  377. if(mode == 'R'){
  378. Cache[pos] = 1;
  379. Cache[pos] = Cache[pos] << 31;
  380. }
  381. else{
  382. Cache[pos] = 3;
  383. Cache[pos] = Cache[pos] << 30;
  384. }
  385.  
  386. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  387. printf("%d", Cache[pos]);
  388. return 0; //return miss
  389. }
  390. else{
  391. tTag = Cache[pos] << 2; tTag = tTag >> 12;
  392. if(tag == tTag){ // HIT
  393. if(mode == 'R'){
  394. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  395. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  396. }
  397. else{
  398. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  399. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  400. }
  401. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  402. Cache[pos] = Cache[pos] << 10;
  403. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  404. return 1; //return hit
  405. }
  406. if(LRUpos < timer){ //finds the least recently used block in case theres no free block
  407. LRUpos = pos;
  408. }
  409. }
  410. }
  411. //at this point theres no empty block, and no hits, so we use LRU policy
  412. pos = LRUpos;
  413. D = Cache[pos] << 1 >> 31;
  414. V = Cache[pos] >> 31;
  415. aux = tag; aux <<= 10;
  416. timer = cycles;
  417. aux = aux | timer; //aux OR timer, coloca tag e timer da LRU nos bits
  418.  
  419. if(D == 1){ extra = 1; }
  420. if(mode == 'R'){
  421. Cache[pos] = 1; Cache[pos] = Cache[pos] << 31;
  422. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  423. }
  424. else{
  425. Cache[pos] = 3; Cache[pos] = Cache[pos] << 30;
  426. Cache[pos] = Cache[pos] | aux; // V - D - tag - LRU
  427. }
  428. Cache[pos] = Cache[pos] >> 10; //Limpa LRU
  429. Cache[pos] = Cache[pos] << 10;
  430. Cache[pos] = Cache[pos] | cycles; //atualiza LRU
  431. return 0;
  432. }
  433.  
  434.  
  435. //this function is taken from: https://stackoverflow.com/questions/10156409/convert-hex-string-char-to-int
  436. //
  437. uint32_t hex2int(char *hex) {
  438. uint32_t val = 0;
  439. while (*hex) {
  440. // get current character then increment
  441. uint8_t byte = *hex++;
  442. // transform hex character to the 4bit equivalent number, using the ascii table indexes
  443. if (byte >= '0' && byte <= '9') byte = byte - '0';
  444. else if (byte >= 'a' && byte <='f') byte = byte - 'a' + 10;
  445. else if (byte >= 'A' && byte <='F') byte = byte - 'A' + 10;
  446. // shift 4 to make space for new digit, and add the 4 bits of the new digit
  447. val = (val << 4) | (byte & 0xF);
  448. }
  449. return val;
  450. }
  451. void getValues(uint32_t*tag,uint32_t*index,uint32_t tagsize,uint32_t indexsize,uint32_t end){
  452. *tag = end >> (32-tagsize); //32 - (tagsize + indexsize) -> calculo do OFFSET
  453. *index = end << tagsize >> (32 - ((tagsize + indexsize) + tagsize));
  454. return;
  455. }
  456. int getBlockPos(int index,int num_blocks){
  457. return index % num_blocks;
  458. }
  459. void setValues(uint32_t* tag, uint32_t* index, uint32_t size,struct cache * configs){
  460. int offset = (int) log2((double)configs->block);
  461. *index = (int) log2((double)configs->num_blocks);
  462. *tag = 32 - (*index + offset);
  463. }
  464. /*
  465. setStrings(str1,str2,stream);
  466. void setStrings(char * str1, char * str2, char * stream){ //Funcao para separar os endereços de entrada
  467. int i; char *p;
  468. p = stream;
  469. for(i=0; *p != '\n'; p++,i++){
  470. str1[i] = *p;
  471. }
  472. p = stream+11;
  473. for(i=0; *p != '\n'; p++,i++){
  474. str2[i] = *p;
  475. }
  476. str1[i] = '\0';
  477. str2[i] = '\0';
  478. return;
  479. }*/
  480. /*
  481. int _hash(char * str, int num_blocks, int assoc){
  482. int i, res, target_block;
  483. char *p, op[3];
  484. char q = str + 7;
  485. for(i=0;i<3;i++,p++){
  486. op[i] = *p;
  487. }
  488. res = (int) strtol(op, NULL, 16); //converts string to long int, third arg selects base.
  489.  
  490.  
  491. target_block = res % assoc;
  492. res = res % num_blocks;
  493. if(assoc == 1)
  494. return res;
  495. else
  496. return target_block;
  497. }*/
  498. int cacheSize(int assoc, int num_blocks, int block){
  499. printf("here");
  500. return assoc * (4*block) * num_blocks;
  501. }
  502. void startStats(struct stats * sim){
  503. //sim->cycles = malloc(sizeof(unsigned long));
  504. (*sim).hits = malloc(sizeof(unsigned long));
  505. (*sim).misses = malloc(sizeof(unsigned long));
  506. (*sim).cycles = 0;
  507. *(*sim).hits = 0;
  508. *(*sim).misses = 0;
  509. return;
  510. }
  511. void LRUstart(uint32_t * Cache, uint32_t size){
  512. uint32_t i;
  513. for(i = 0 ; i<size ; i++){
  514. Cache[i] = i;
  515. }
  516. }
  517.  
  518. int acessCache(struct cache * configs,struct stats * sim,uint32_t * Cache, uint32_t end,int num_configs, uint32_t mem_lat,char mode){
  519. uint32_t tag,index,tagsize,indexsize,size=0,pos,extra=0;
  520.  
  521. setValues(&tagsize,&indexsize,size, configs);
  522. getValues(&tag,&index,tagsize,indexsize,end);
  523.  
  524.  
  525. // if(num_configs == 1){ //ACESSO L1
  526. //end = _hash(str1,configs->num_blocks,configs->assoc);
  527.  
  528. pos = getBlockPos(index,configs->num_blocks);
  529. printf("\npos=%d\n", pos);
  530. if(configs->assoc == 1){ //mapeando direto
  531. if(dirMapped(Cache,tag,pos,sim->cycles,mode,extra)){ //hit
  532. // sim->cycles += configs->lat;
  533. // *(*sim).hits += 1;
  534. return 1;
  535. }
  536.  
  537. else{//miss
  538. if(extra == 1){(*sim).cycles += mem_lat;} //if it was a miss in a writtenblock then writeback policy
  539. // (*sim).cycles += 1;
  540. // (*sim).cycles += mem_lat;
  541. // *(*sim).misses += 1;
  542. return 0;
  543. }
  544. extra = 0;
  545. }
  546. else if(configs->assoc == configs->num_blocks){ //fully associative
  547. if(fullyAssoc(Cache,tag,0,sim->cycles,mode,extra,configs->num_blocks)){ //hit
  548. // sim->cycles += configs->lat;
  549. // *(*sim).hits += 1;
  550. }
  551. else{ //miss
  552. // (*sim).cycles += 1;
  553. // (*sim).cycles += mem_lat;
  554. // *(*sim).misses += 1;
  555. }
  556. }
  557. else{ //associativo
  558. if(assocMapped(Cache,tag,pos,sim->cycles,mode,extra,configs)){
  559. sim->cycles += configs->lat;
  560. // *(*sim).hits += 1;
  561. return 1;
  562. }
  563. else{//miss
  564. if(extra == 1){(*sim).cycles += mem_lat;} //if it was a miss in a writtenblock then writeback policy
  565. // (*sim).cycles += 1;
  566. // (*sim).cycles += mem_lat;
  567. // *(*sim).misses += 1;
  568. return 0;
  569. }
  570. }
  571. // }
  572. // else{ //ACESSO l2
  573. // }
  574. return 0;
  575. }
  576.  
  577. #endif // _SIM_H_
  578.  
  579.  
  580.  
  581. /* if(acessCache(configs,sim,Cache,end,num_configs,mem_lat,str[0])){ //hit na l1: update LRU and leave
  582.  
  583. }
  584. else{
  585. if(acessCache(p,sim,Cache,end,num_configs,mem_lat,str[0])) //hit na l2: updates l2 LRU and bring it to l1
  586. {
  587. push2l1(configs,sim,Cache,end,num_configs,mem_lat,str[0]);
  588. }
  589. else{
  590. push2l1(configs,sim,Cache,end,num_configs,mem_lat,str[0]);
  591. push2l2(configs,sim,Cache,end,num_configs,mem_lat,str[0]);
  592. }*/
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!