// apb_master.sv
// An APB bus master unit

module apb_master #
(
    // parameters
    parameter DATA_WIDTH = 16,
    parameter ADDR_WIDTH = 16

)
(
    // global
    input  logic                    pclk,
    input  logic                    preset_n,

    // to/from cpu
    svif_mem.slave                  cpu_if,

    //to slaves
    output logic [ADDR_WIDTH-1:0]   paddr,
    output logic                    pwrite,
    output logic [DATA_WIDTH-1:0]   pwdata,
    output logic                    penable,

    //from interconnect multiplexer
    input  logic [DATA_WIDTH-1:0]   prdata,
    input  logic                    pready,
    input  logic                    pslverr

);

// as all peripherals are memory mapped, psel is used to control the multiplexer for the slave responses

enum logic[1:0] {IDLE, SETUP, ACCESS} state;

//next state logic
always_ff @(posedge pclk, negedge preset_n)
if(!preset_n)
begin
    state <= IDLE;
end
else
begin
    case(state)
        IDLE:   if(cpu_if.req)
                    state <= SETUP;
        SETUP:  state <= ACCESS;
        ACCESS: if(pready)
                    if(cpu_if.req)
                        state <= SETUP;
                    else
                        state <= IDLE;
        default: state <= IDLE;
    endcase
end

//output logic
always_comb
begin
    penable = 0;

    pwrite = cpu_if.write;
    pwdata = cpu_if.wdata;
    paddr  = cpu_if.addr;

    cpu_if.rdata = prdata;
    cpu_if.done  = pready;
    //pslverr is used only in simulation

    case(state)
        IDLE:   begin end
        SETUP:  begin end
        ACCESS: begin penable = '1; end
        default: begin end

    endcase
end


endmodule