`timescale 1ns / 1ps
module udp_former_v3(
        input logic CLK                 ,
        input logic RESET               ,
        input logic[47 : 0] HOST_MAC    ,
        input logic[31 : 0] HOST_IP     ,
        input logic[15 : 0] HOST_PORT   ,
        input logic[15 : 0] DEST_PORT   ,

        input logic[7 : 0]  S_AXIS_TDATA,
        input logic S_AXIS_TVALID       ,
        output logic S_AXIS_TREADY      = 1'b0,
        input logic S_AXIS_TLAST        ,

        output logic[7 : 0] M_AXIS_TDATA = '{default:0},
        output logic M_AXIS_TVALID      = 1'b0,
        input logic M_AXIS_TREADY       ,
        output logic M_AXIS_TLAST       = 1'b0
    );
    typedef enum {
        IDLE,
        HEAD,
        DATA
    } FORMER;
    FORMER former = IDLE;

    logic[8:0] din_in = '{default:0};
    logic wr_en_in = 1'b0;
    logic rd_en_in = 1'b0;
    logic[8:0] dout_in;
    logic full_in;
    logic almost_full_in;
    logic almost_empty_in;
    logic empty_in;

     logic[8:0] din_out = '{default:0};
     logic wr_en_out = 1'b0;
     logic rd_en_out = 1'b0;
     logic[8:0] dout_out;
     logic full_out;
     logic almost_full_out;
     logic almost_empty_out;
     logic empty_out;

    ila_1 ila(
        CLK,
        {
            S_AXIS_TDATA,
            S_AXIS_TVALID,
            S_AXIS_TREADY,
            S_AXIS_TLAST,
            din_out,
            wr_en_out,
            rd_en_out,
            dout_out,
            full_out,
            almost_full_out,
            almost_empty_out,
            empty_out
        },
        {
            M_AXIS_TDATA,
            M_AXIS_TVALID,
            M_AXIS_TREADY,
            M_AXIS_TLAST,
            din_in,
            wr_en_in,
            rd_en_in,
            dout_in,
            full_in,
            almost_full_in,
            almost_empty_in,
            empty_in,
            former
        }
    );



    logic[15:0] counter_data_for_fifo_in = '{default:0};
    logic[15:0] counter_data_for_data_form = '{default:0};
    logic[15:0] ip_len = '{default:0};

    logic [5:0] byte_counter = '{default:0};

    logic IPV4_CALC_START;
    logic IPV4_CALC_CLEAR ;
    logic[15:0] IPV4_CHKSUM ;
    logic IPV4_DONE ;

    logic[14:0] data_count;
    logic[15:0] local_data_count = '{default:0};
    fifo_generator_0 fifo_in(
        .clk(CLK),
        .rst(RESET),
        .din(din_in),
        .wr_en(wr_en_in),
        .rd_en(rd_en_in),
        .dout(dout_in),
        .full(full_in),
        .almost_full(almost_full_in),
        .almost_empty(almost_empty_in),
        .empty(empty_in),
        .data_count(data_count)
    );
    fifo_generator_1 fifo_out(
        .clk(CLK),
        .rst(RESET),
        .din(din_out),
        .wr_en(wr_en_out),
        .rd_en(rd_en_out),
        .dout(dout_out),
        .full(full_out),
        .almost_full(almost_full_out),
        .empty(empty_out)
    );
    ipv4_check_sum_v1_sync_8t checker_sum(
        .CLK(CLK),
        .RESET(RESET),
        .IP_START_CALC(IPV4_CALC_START),
        .IP_CLEAR_CALC(IPV4_CALC_CLEAR),
        .IP_ID('h0000),
        .IP_VER_LEN('h4500),
        .IP_TOTAL_SIZE(ip_len),
        .IP_PROTOCOL_TYPE('h11),
        .IP_SRC_ADDR(HOST_IP),
        .IP_DEST_ADDR('hffffa8c0),
        .IP_TTL('h00),
        .CHECK_SUM(IPV4_CHKSUM),
        .SUM_READY(IPV4_DONE)
    );

    // always_comb begin

    //  din_in = {S_AXIS_TLAST, S_AXIS_TDATA};
    //  wr_en_in = S_AXIS_TVALID;
    //  if((former == IDLE) & ~RESET)
    //      S_AXIS_TREADY = 1'b1;
    //  else S_AXIS_TREADY = 1'b0;

    //  M_AXIS_TVALID = ~empty_out;
    //  M_AXIS_TLAST = dout_out[8];
    //  M_AXIS_TDATA = dout_out[7:0];
    //  if((~empty_out) & M_AXIS_TREADY)
    //      rd_en_out = 1'b1;
    //  else rd_en_out = 1'b0;

    //  IPV4_CALC_START = S_AXIS_TLAST;

    //  if(S_AXIS_TLAST)begin
    //      ip_len = data_count + 40;
    //      local_data_count = data_count;
    //  end

    //  if(former != HEAD)
    //      IPV4_CALC_CLEAR = 1'b1;
    //  else
    //      IPV4_CALC_CLEAR = 1'b0;
    // end
    always @(posedge CLK) begin
        if(S_AXIS_TREADY & S_AXIS_TVALID) begin
            din_in <= {S_AXIS_TLAST, S_AXIS_TDATA};
            wr_en_in <= S_AXIS_TVALID;
        end

        if(former == IDLE)
            S_AXIS_TREADY <= 1'b1;
        else S_AXIS_TREADY <= 1'b0;

        M_AXIS_TVALID <= ~empty_out;
        M_AXIS_TLAST <= dout_out[8];
        M_AXIS_TDATA <= dout_out[7:0];
        if((~empty_out) & M_AXIS_TREADY)
            rd_en_out <= 1'b1;
        else rd_en_out <= 1'b0;

        IPV4_CALC_START <= S_AXIS_TLAST;

        if(S_AXIS_TLAST)begin
            ip_len <= data_count + 40;
            local_data_count <= data_count;
        end

        if(former != HEAD)
            IPV4_CALC_CLEAR = 1'b1;
        else
            IPV4_CALC_CLEAR = 1'b0;
        if(S_AXIS_TLAST)begin
            former <= HEAD;
        end
        unique case (former)
            HEAD: begin
                byte_counter <= byte_counter + 1;
                unique case (byte_counter)
                    0:      begin
                        din_out <= 'hff;
                        wr_en_out <= 1'b1;
                    end
                    1:      din_out <= 'hff                                    ;
                    2:      din_out <= 'hff                                    ;
                    3:      din_out <= 'hff                                    ;
                    4:      din_out <= 'hff                                    ;
                    5:      din_out <= 'hff                                    ;
                    6:      din_out <= HOST_MAC            [ 7 : 0]            ;
                    7:      din_out <= HOST_MAC            [15 : 8]            ;
                    8:      din_out <= HOST_MAC            [23 : 16]           ;
                    9:      din_out <= HOST_MAC            [31 : 24]           ;
                    10:     din_out <= HOST_MAC            [39 : 32]           ;
                    11:     din_out <= HOST_MAC            [47 : 40]           ;
                    12:     din_out <= 'h08                                    ;
                    13:     din_out <= 'h00                                    ;
                    14:     din_out <= 'h45                                    ;
                    15:     din_out <= 'h00                                    ;
                    16:     din_out <= ip_len        [15:8]            ;
                    17:     din_out <= ip_len        [7:0]             ;
                    18:     din_out <= 'h00                                    ;
                    19:     din_out <= 'h00                                    ;
                    20:     din_out <= 'h00                                    ;
                    21:     din_out <= 'h00                                    ;
                    22:     din_out <= 'h00                                 ;
                    23:     din_out <= 'h11                            ;
                    24:     din_out <= IPV4_CHKSUM         [15 :  8]           ;
                    25:     din_out <= IPV4_CHKSUM         [ 7 :  0]           ;
                    26:     din_out <= HOST_IP             [ 7 :  0]           ;
                    27:     din_out <= HOST_IP             [15 :  8]           ;
                    28:     din_out <= HOST_IP             [23 : 16]           ;
                    29:     din_out <= HOST_IP             [31 : 24]           ;
                    30:     din_out <= 'hC0                                    ;
                    31:     din_out <= 'hA8                                    ;
                    32:     din_out <= 'hff                                    ;
                    33:     din_out <= 'hff                                    ;
                    34:     din_out <= HOST_PORT           [ 7 : 0]            ;
                    35:     din_out <= HOST_PORT           [15 : 8]            ;
                    36:     din_out <= DEST_PORT           [ 7 : 0]            ;
                    37:     din_out <= DEST_PORT           [15 : 8]            ;
                    38:     din_out <= local_data_count[15:8]              ;
                    39:     begin
                        din_out <= local_data_count[7:0];
                        former <= DATA;
                        byte_counter <= 0;
                        rd_en_in <= 1'b1;
                    end
                endcase;
            end
            DATA: begin
                din_out <= dout_in;
                if(din_out[8] == 1)begin
                    rd_en_in <= 1'b0;
                    wr_en_out <= 1'b0;
                    former <= IDLE;
                end
            end
        endcase;
    end

endmodule