NOTICE:  BL2: v1.5(release):lx2160a-early-access-bsp0.5
NOTICE:  BL2: Built : 13:40:45, Feb 24 2019
NOTICE:  UDIMM M471A4G43MB1-CTD
NOTICE:  BL2: v1.5(release):lx2160a-early-access-bsp0.5
NOTICE:  BL2: Built : 13:40:45, Feb 24 2019
NOTICE:  UDIMM M471A4G43MB1-CTD
NOTICE:  DDR4 UDIMM with 2-rank 64-bit bus (x8)

NOTICE:  64 GB DDR4, 64-bit, CL=19, ECC off, 256B, CS0+CS1
NOTICE:  BL2: Booting BL31
NOTICE:  BL31: v1.5(release):lx2160a-early-access-bsp0.5
NOTICE:  BL31: Built : 13:40:48, Feb 24 2019
NOTICE:  Welcome to LX2160 BL31 Phase


U-Boot 2018.09-dirty (Feb 24 2019 - 13:40:37 +0200)

SoC:  LX2160ACE Rev1.0 (0x87360010)
Clock Configuration:
       CPU0(A72):1900 MHz  CPU1(A72):1900 MHz  CPU2(A72):1900 MHz
       CPU3(A72):1900 MHz  CPU4(A72):1900 MHz  CPU5(A72):1900 MHz
       CPU6(A72):1900 MHz  CPU7(A72):1900 MHz  CPU8(A72):1900 MHz
       CPU9(A72):1900 MHz  CPU10(A72):1900 MHz  CPU11(A72):1900 MHz
       CPU12(A72):1900 MHz  CPU13(A72):1900 MHz  CPU14(A72):1900 MHz
       CPU15(A72):1900 MHz
       Bus:      600  MHz  DDR:      2600 MT/s
Reset Configuration Word (RCW):
       00000000: 4c6b6b30 244c004c 00000000 00000000
       00000010: 00000000 0e010000 00000000 00000000
       00000020: 01a001a0 00002580 00000000 00000086
       00000030: 00000000 00000000 00000000 00000000
       00000040: 00000000 00000000 00000000 00000000
       00000050: 00000000 00000000 00000000 00000000
       00000060: 00000000 00000000 00027000 00000000
       00000070: 08830001 001d1020
Model: SolidRun LX2160ACEX7 COM express type 7 based board
Board: LX2160ACE Rev1.0-CEX7, SD
SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz
SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz
I2C:   ready
DRAM:  63.9 GiB
DDR    63.9 GiB (DDR4, 64-bit, CL=19, ECC off)
       DDR Controller Interleaving Mode: 256B
       DDR Chip-Select Interleaving Mode: CS0+CS1
Using SERDES1 Protocol: 3 (0x3)
Using SERDES2 Protocol: 4 (0x4)
Using SERDES3 Protocol: 2 (0x2)
MMC:   clock is enabled (400000Hz)
clock is enabled (400000Hz)
FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... clock is disabled (0Hz)
selecting mode MMC legacy (freq : 0 MHz)
clock is enabled (400000Hz)
selecting mode MMC legacy (freq : 25 MHz)
sd card: widths [4, 1] modes [SD Legacy, SD High Speed (50MHz)]
host: widths [4, 1] modes [MMC legacy, SD Legacy, MMC High Speed (26MHz), SD Hig                                             h Speed (50MHz), MMC High Speed (52MHz)]
trying mode SD High Speed (50MHz) width 4 (at 50 MHz)
selecting mode SD High Speed (50MHz) (freq : 50 MHz)
clock is enabled (400000Hz)
*** Warning - bad CRC, using default environment

In:    serial_pl01x
Out:   serial_pl01x
Err:   serial_pl01x
Net:   PCIe0: pcie@3400000 disabled
PCIe1: pcie@3500000 Root Complex: no link
PCIe2: pcie@3600000 Root Complex: no link
PCIe3: pcie@3700000 Root Complex: no link
PCIe4: pcie@3800000 Root Complex: no link
PCIe5: pcie@3900000 disabled
DPMAC3@xgmii
Warning: DPMAC3@xgmii (eth0) using random MAC address - 5e:1d:09:9e:87:f1
, DPMAC4@xgmii
Warning: DPMAC4@xgmii (eth1) using random MAC address - 66:46:f4:3e:6e:f9
, DPMAC5@xgmii
Warning: DPMAC5@xgmii (eth2) using random MAC address - 6e:4e:dd:44:e2:f5
, DPMAC6@xgmii
Warning: DPMAC6@xgmii (eth3) using random MAC address - 7a:67:60:03:73:01
, DPMAC17@rgmii-id [PRIME]
Warning: DPMAC17@rgmii-id (eth4) using random MAC address - 52:6e:8c:36:2e:dd


MMC read: dev # 0, block # 20480, count 4096 ... 4096 blocks read: OK

MMC read: dev # 0, block # 28672, count 4096 ... 4096 blocks read: OK



Called do_fsl_mc



Rabeeh - checking image format at 0000000080000000
In genimg_get_format 869
In genimg_get_format 872
In genimg_get_format 877
Returned type 2
In fit_check_format 1461
In fit_check_format 1467
In fit_check_format 1478
In fit_check_format 1486
crc32+
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 10.14.0, boot status: 0x1)




called mc_init_object