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- --------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 10:35:16 01/29/2020
- -- Design Name:
- -- Module Name: /home/speaker/xilinx/14.7/ISE_DS/progetto_Td/prog_td_tb.vhd
- -- Project Name: progetto_Td
- -- Target Device:
- -- Tool versions:
- -- Description:
- --
- -- VHDL Test Bench Created by ISE for module: progetto_TD_vhdl
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- -- Notes:
- -- This testbench has been automatically generated using types std_logic and
- -- std_logic_vector for the ports of the unit under test. Xilinx recommends
- -- that these types always be used for the top-level I/O of a design in order
- -- to guarantee that the testbench will bind correctly to the post-implementation
- -- simulation model.
- --------------------------------------------------------------------------------
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- USE ieee.numeric_std.ALL;
- ENTITY prog_td_tb IS
- END prog_td_tb;
- ARCHITECTURE behavior OF prog_td_tb IS
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT progetto_TD_vhdl
- PORT(
- buttonA : IN std_logic;
- buttonB : IN std_logic;
- sensorA : IN std_logic;
- sensorB : IN std_logic;
- sensorC : IN std_logic;
- md_detection : IN std_logic;
- doorA : OUT std_logic;
- doorB : OUT std_logic;
- alarm : OUT std_logic;
- clk : IN std_logic;
- rst : IN std_logic
- );
- END COMPONENT;
- --Inputs
- signal buttonA : std_logic := '0';
- signal buttonB : std_logic := '0';
- signal sensorA : std_logic := '0';
- signal sensorB : std_logic := '0';
- signal sensorC : std_logic := '0';
- signal md_detection : std_logic := '0';
- signal clk : std_logic := '0';
- signal rst : std_logic := '0';
- --signal timeover : std_logic :='0'; --aggiunto-----------------------------------
- --Outputs
- signal doorA : std_logic;
- signal doorB : std_logic;
- signal alarm : std_logic;
- -- Clock period definitions
- constant clk_period : time := 10 ns;
- BEGIN
- -- Instantiate the Unit Under Test (UUT)
- uut: progetto_TD_vhdl PORT MAP (
- buttonA => buttonA,
- buttonB => buttonB,
- sensorA => sensorA,
- sensorB => sensorB,
- sensorC => sensorC,
- md_detection => md_detection,
- doorA => doorA,
- doorB => doorB,
- alarm => alarm,
- clk => clk,
- rst => rst
- );
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns
- rst<='1';
- wait for 10 ns;
- rst<='0';
- wait for 10 ns;
- wait for clk_period*10;
- -- insert stimulus here
- --A TO B
- --test so
- buttonB<='0';
- buttonA<='0';
- wait for 10 ns;
- buttonB<='0';
- buttonA<='1';
- wait for 10 ns;
- --test s1
- sensorA<='1';
- buttonA<='0';
- wait for 10 ns;
- sensorC<='1';
- sensorA<='0';
- wait for 10 ns;
- --test s2
- sensorC<='1';
- wait for 10 ns;
- sensorC<='1';
- md_detection<='0';
- wait for 10 ns;
- --test s3
- sensorC<='1';
- wait for 10 ns;
- sensorC<='0';
- sensorB<='1';
- wait for 10 ns;
- sensorC<='0';
- sensorB<='0';
- wait for 10 ns;
- --TEST FAKE ENTRANCE
- --test s0
- buttonB<='0';
- buttonA<='0';
- wait for 10 ns;
- buttonB<='0';
- buttonA<='1';
- wait for 10 ns;
- --test s1
- buttonA<='0';
- wait for 10 ns;
- --timeover<='1';
- sensorA<='0';
- sensorC<='0';
- wait for 20 ns;
- --timeover<='0';
- wait for 10 ns;
- --TEST ALARM
- --test s0
- buttonB<='0';
- buttonA<='0';
- wait for 10 ns;
- buttonB<='0';
- buttonA<='1';
- wait for 10 ns;
- --test s1
- sensorA<='1';
- buttonA<='0';
- wait for 10 ns;
- sensorC<='1';
- sensorA<='0';
- wait for 10 ns;
- --test s2
- sensorC<='1';
- wait for 10 ns;
- sensorC<='1';
- md_detection<='1';
- wait for 10 ns;
- --test s4
- sensorC<='1';
- md_detection<='1';
- wait for 10 ns;
- sensorC<='0';
- md_detection<='0';
- sensorA<='1';
- wait for 10 ns;
- sensorC<='0';
- md_detection<='0';
- sensorA<='0';
- wait for 10 ns;
- --test B to A
- --test s0
- buttonB<='0';
- buttonA<='0';
- wait for 10 ns;
- buttonB<='1';
- wait for 10 ns;
- --test s5
- buttonB<='0';
- sensorB<='1';
- wait for 10 ns;
- --test s6
- sensorC<='1';
- wait for 10 ns;
- --timeover<='1';
- wait for 10 ns;
- --test s7
- sensorC<='1';
- sensorA<='0';
- --timeover<='0';
- wait for 10 ns;
- sensorC<='0';
- sensorA<='1';
- wait for 10 ns;
- sensorC<='0';
- sensorA<='0';
- wait for 10 ns;
- --FAKE EXIT
- --test s0
- buttonB<='0';
- buttonA<='0';
- wait for 10 ns;
- buttonB<='1';
- wait for 10 ns;
- --test s5
- buttonB<='0';
- wait for 10 ns;
- sensorB<='0';
- --timeover<='1';
- sensorC<='0';
- wait for 10 ns;
- --timeover<='0';
- wait for 10 ns;
- wait;
- end process;
- END;
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