Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
    Info: Processing started: Tue Aug 08 17:08:20 2017
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SDRAM_VGA -c SDRAM_VGA
Info (20030): Parallel compilation is enabled and will use 3 of the 3 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file sdram_controller.v
    Info (12023): Found entity 1: SDRAM_CONTROLLER
Info (12021): Found 1 design units, including 1 entities, in source file pllvga.v
    Info (12023): Found entity 1: PLLVGA
Info (12021): Found 1 design units, including 1 entities, in source file provapll.v
    Info (12023): Found entity 1: provapll
Info (12021): Found 1 design units, including 1 entities, in source file pll2.v
    Info (12023): Found entity 1: pll2
Warning (12125): Using design file sdram_vga.v, which is not specified as a design file for the current project, but contains definitions for 4 design units and 4 entities in project
    Info (12023): Found entity 1: SDRAM_VGA
    Info (12023): Found entity 2: clk_div
    Info (12023): Found entity 3: FFD
    Info (12023): Found entity 4: button
Info (12127): Elaborating entity "SDRAM_VGA" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at sdram_vga.v(284): object "currentCommand" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(287): truncated value with size 24 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(294): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(301): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(309): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(310): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(311): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(312): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(314): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(315): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(316): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(317): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(319): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(320): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(321): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(322): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(324): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(325): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(326): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(327): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(329): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(330): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(331): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(332): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(334): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(335): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(336): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(337): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(339): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(340): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(341): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(342): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(344): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(345): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(346): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sdram_vga.v(347): truncated value with size 32 to match size of target (6)
Warning (10030): Net "arrayChar[1][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[1][2..3]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[1][7..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[2][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[2][2..3]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[2][7..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[3][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[3][2..3]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[3][7..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[4][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[4][2..3]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[4][7..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[5][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[5][2..3]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[5][7..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[6][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[6][2..3]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[6][6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[6][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[7][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[7][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[7][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[8][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[8][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[8][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[9][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[9][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[9][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[10][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[10][2..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[11][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[11][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[11][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[12][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[12][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[12][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[13][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[13][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[13][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[14][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[14][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[14][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[15][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[15][2..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[16][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[16][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[16][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[17][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[17][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[17][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[18][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[18][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[18][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[19][0]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[19][2..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[19][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[21][0..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[21][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[20]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[22][0..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[22][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[23][0..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[23][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[24][0..6]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[24][9..59]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "arrayChar[25..105]" at sdram_vga.v(194) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "INData[1..7]" at sdram_vga.v(274) has no driver or initial value, using a default initial value '0'
Warning (10034): Output port "HEX0" at sdram_vga.v(57) has no driver
Warning (10034): Output port "HEX1" at sdram_vga.v(58) has no driver
Warning (10034): Output port "HEX2" at sdram_vga.v(59) has no driver
Warning (10034): Output port "HEX3" at sdram_vga.v(60) has no driver
Warning (10034): Output port "HEX4" at sdram_vga.v(61) has no driver
Warning (10034): Output port "HEX5" at sdram_vga.v(62) has no driver
Warning (10034): Output port "LEDR[6]" at sdram_vga.v(68) has no driver
Warning (10034): Output port "LEDR[4..2]" at sdram_vga.v(68) has no driver
Warning (10034): Output port "GSENSOR_CS_N" at sdram_vga.v(81) has no driver
Warning (10034): Output port "GSENSOR_SCLK" at sdram_vga.v(83) has no driver
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "font" into its bus
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "arrayChar" into its bus
Info (12128): Elaborating entity "PLLVGA" for hierarchy "PLLVGA:pll1"
Info (12128): Elaborating entity "altpll" for hierarchy "PLLVGA:pll1|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "PLLVGA:pll1|altpll:altpll_component"
Info (12133): Instantiated megafunction "PLLVGA:pll1|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "2000"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "1007"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "2000"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "1007"
    Info (12134): Parameter "clk1_phase_shift" = "9930"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "MAX 10"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=PLLVGA"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/pllvga_altpll.v
    Info (12023): Found entity 1: PLLVGA_altpll
Info (12128): Elaborating entity "PLLVGA_altpll" for hierarchy "PLLVGA:pll1|altpll:altpll_component|PLLVGA_altpll:auto_generated"
Info (12128): Elaborating entity "pll2" for hierarchy "pll2:test"
Info (12128): Elaborating entity "altpll" for hierarchy "pll2:test|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "pll2:test|altpll:altpll_component"
Info (12133): Instantiated megafunction "pll2:test|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "1"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "2"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "1"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "2"
    Info (12134): Parameter "clk1_phase_shift" = "3000"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "MAX 10"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll2"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/pll2_altpll.v
    Info (12023): Found entity 1: pll2_altpll
Info (12128): Elaborating entity "pll2_altpll" for hierarchy "pll2:test|altpll:altpll_component|pll2_altpll:auto_generated"
Info (12128): Elaborating entity "button" for hierarchy "button:breset_n"
Info (12128): Elaborating entity "FFD" for hierarchy "button:breset_n|FFD:m"
Info (12128): Elaborating entity "SDRAM_CONTROLLER" for hierarchy "SDRAM_CONTROLLER:miaRam"
Warning (10036): Verilog HDL or VHDL warning at SDRAM_CONTROLLER.v(147): object "initStarted" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at SDRAM_CONTROLLER.v(149): object "currentState" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at SDRAM_CONTROLLER.v(150): object "currentWait" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at SDRAM_CONTROLLER.v(191): object "emptyState" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at SDRAM_CONTROLLER.v(192): object "fullState" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at SDRAM_CONTROLLER.v(200): object "fullRead" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at SDRAM_CONTROLLER.v(209): object "emptyWrite" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(245): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(281): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(307): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(309): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(311): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(312): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(313): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(315): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(317): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(319): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(321): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(323): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(325): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(327): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(329): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(331): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(333): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(335): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(337): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(339): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(341): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(343): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(345): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(347): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(348): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(349): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(361): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(363): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(365): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(366): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(367): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(369): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(371): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(373): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(374): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(375): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(377): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(379): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(381): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(383): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(385): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(387): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(389): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(391): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(393): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(395): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(397): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(399): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(401): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(403): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(405): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(407): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(415): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(418): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(419): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(421): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(424): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(425): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(426): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(431): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(433): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(439): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(444): truncated value with size 16 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(459): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(460): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(461): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(467): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(469): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(471): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(472): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(473): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(477): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(479): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(481): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(482): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(483): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(516): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(536): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(559): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(581): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(589): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(593): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(609): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(627): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(634): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(636): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(637): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(638): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at SDRAM_CONTROLLER.v(652): truncated value with size 32 to match size of target (5)
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1q14.tdf
    Info (12023): Found entity 1: altsyncram_1q14
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_h7a.tdf
    Info (12023): Found entity 1: decode_h7a
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_o3b.tdf
    Info (12023): Found entity 1: mux_o3b
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_i7c.tdf
    Info (12023): Found entity 1: mux_i7c
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_3af.tdf
    Info (12023): Found entity 1: decode_3af
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_hrh.tdf
    Info (12023): Found entity 1: cntr_hrh
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_hrb.tdf
    Info (12023): Found entity 1: cmpr_hrb
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_6mi.tdf
    Info (12023): Found entity 1: cntr_6mi
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_7rh.tdf
    Info (12023): Found entity 1: cntr_7rh
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_irb.tdf
    Info (12023): Found entity 1: cmpr_irb
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_odi.tdf
    Info (12023): Found entity 1: cntr_odi
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_drb.tdf
    Info (12023): Found entity 1: cmpr_drb
Info (12033): Analysis and Synthesis generated SignalTap II or debug node instance "auto_signaltap_0"
Info (11170): Starting IP generation for the debug fabric: alt_sld_fab.
Info (11172): 2017.08.08.17:08:50 Progress: Loading sld39f46d90/alt_sld_fab_wrapper_hw.tcl
Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG
Info (11172): Alt_sld_fab: Generating alt_sld_fab "alt_sld_fab" for QUARTUS_SYNTH
Info (11172): Alt_sld_fab: "alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab"
Info (11172): Presplit: "alt_sld_fab" instantiated altera_super_splitter "presplit"
Info (11172): Splitter: "alt_sld_fab" instantiated altera_sld_splitter "splitter"
Info (11172): Sldfabric: "alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric"
Info (11172): Ident: "alt_sld_fab" instantiated altera_connection_identification_hub "ident"
Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 6 modules, 6 files
Info (11171): Finished IP generation for the debug fabric: alt_sld_fab.
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld39f46d90/alt_sld_fab.v
    Info (12023): Found entity 1: alt_sld_fab
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld39f46d90/submodules/alt_sld_fab_alt_sld_fab.v
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld39f46d90/submodules/alt_sld_fab_alt_sld_fab_ident.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_ident
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld39f46d90/submodules/alt_sld_fab_alt_sld_fab_presplit.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_presplit
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sld39f46d90/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd
    Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld39f46d90/submodules/alt_sld_fab_alt_sld_fab_splitter.sv
    Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_splitter
Info (278001): Inferred 7 megafunctions from design logic
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "SDRAM_CONTROLLER:miaRam|Div0"
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div0"
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Mod0"
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div1"
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div2"
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div3"
    Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "Div4"
Info (12130): Elaborated megafunction instantiation "SDRAM_CONTROLLER:miaRam|lpm_divide:Div0"
Info (12133): Instantiated megafunction "SDRAM_CONTROLLER:miaRam|lpm_divide:Div0" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHN" = "32"
    Info (12134): Parameter "LPM_WIDTHD" = "17"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_avl.tdf
    Info (12023): Found entity 1: lpm_divide_avl
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_cnh.tdf
    Info (12023): Found entity 1: sign_div_unsign_cnh
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_2le.tdf
    Info (12023): Found entity 1: alt_u_div_2le
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_t3c.tdf
    Info (12023): Found entity 1: add_sub_t3c
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_u3c.tdf
    Info (12023): Found entity 1: add_sub_u3c
Info (12130): Elaborated megafunction instantiation "lpm_divide:Div0"
Info (12133): Instantiated megafunction "lpm_divide:Div0" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHN" = "32"
    Info (12134): Parameter "LPM_WIDTHD" = "11"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_sco.tdf
    Info (12023): Found entity 1: lpm_divide_sco
Info (12021): Found 1 design units, including 1 entities, in source file db/abs_divider_1dg.tdf
    Info (12023): Found entity 1: abs_divider_1dg
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_mke.tdf
    Info (12023): Found entity 1: alt_u_div_mke
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_abs_5b9.tdf
    Info (12023): Found entity 1: lpm_abs_5b9
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_abs_8b9.tdf
    Info (12023): Found entity 1: lpm_abs_8b9
Info (12130): Elaborated megafunction instantiation "lpm_divide:Mod0"
Info (12133): Instantiated megafunction "lpm_divide:Mod0" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHN" = "32"
    Info (12134): Parameter "LPM_WIDTHD" = "11"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_v4o.tdf
    Info (12023): Found entity 1: lpm_divide_v4o
Info (12130): Elaborated megafunction instantiation "lpm_divide:Div1"
Info (12133): Instantiated megafunction "lpm_divide:Div1" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHN" = "11"
    Info (12134): Parameter "LPM_WIDTHD" = "32"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_tco.tdf
    Info (12023): Found entity 1: lpm_divide_tco
Info (12021): Found 1 design units, including 1 entities, in source file db/abs_divider_4dg.tdf
    Info (12023): Found entity 1: abs_divider_4dg
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_ske.tdf
    Info (12023): Found entity 1: alt_u_div_ske
Info (12130): Elaborated megafunction instantiation "lpm_divide:Div2"
Info (12133): Instantiated megafunction "lpm_divide:Div2" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHN" = "32"
    Info (12134): Parameter "LPM_WIDTHD" = "32"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_vco.tdf
    Info (12023): Found entity 1: lpm_divide_vco
Info (12130): Elaborated megafunction instantiation "lpm_divide:Div3"
Info (12133): Instantiated megafunction "lpm_divide:Div3" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHN" = "11"
    Info (12134): Parameter "LPM_WIDTHD" = "32"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info (12130): Elaborated megafunction instantiation "lpm_divide:Div4"
Info (12133): Instantiated megafunction "lpm_divide:Div4" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHN" = "32"
    Info (12134): Parameter "LPM_WIDTHD" = "32"
    Info (12134): Parameter "LPM_NREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_DREPRESENTATION" = "SIGNED"
    Info (12134): Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info (13014): Ignored 132 buffer(s)
    Info (13016): Ignored 132 CARRY_SUM buffer(s)
Warning (13039): The following bidirectional pins have no drivers
    Warning (13040): bidirectional pin "GSENSOR_SDI" has no driver
    Warning (13040): bidirectional pin "GSENSOR_SDO" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[0]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[1]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[2]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[3]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[4]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[5]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[6]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[7]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[8]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[9]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[10]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[11]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[12]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[13]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[14]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_IO[15]" has no driver
    Warning (13040): bidirectional pin "ARDUINO_RESET_N" has no driver
    Warning (13040): bidirectional pin "GPIO[0]" has no driver
    Warning (13040): bidirectional pin "GPIO[1]" has no driver
    Warning (13040): bidirectional pin "GPIO[2]" has no driver
    Warning (13040): bidirectional pin "GPIO[3]" has no driver
    Warning (13040): bidirectional pin "GPIO[4]" has no driver
    Warning (13040): bidirectional pin "GPIO[5]" has no driver
    Warning (13040): bidirectional pin "GPIO[6]" has no driver
    Warning (13040): bidirectional pin "GPIO[7]" has no driver
    Warning (13040): bidirectional pin "GPIO[8]" has no driver
    Warning (13040): bidirectional pin "GPIO[9]" has no driver
    Warning (13040): bidirectional pin "GPIO[10]" has no driver
    Warning (13040): bidirectional pin "GPIO[11]" has no driver
    Warning (13040): bidirectional pin "GPIO[12]" has no driver
    Warning (13040): bidirectional pin "GPIO[13]" has no driver
    Warning (13040): bidirectional pin "GPIO[14]" has no driver
    Warning (13040): bidirectional pin "GPIO[15]" has no driver
    Warning (13040): bidirectional pin "GPIO[16]" has no driver
    Warning (13040): bidirectional pin "GPIO[17]" has no driver
    Warning (13040): bidirectional pin "GPIO[18]" has no driver
    Warning (13040): bidirectional pin "GPIO[19]" has no driver
    Warning (13040): bidirectional pin "GPIO[20]" has no driver
    Warning (13040): bidirectional pin "GPIO[21]" has no driver
    Warning (13040): bidirectional pin "GPIO[22]" has no driver
    Warning (13040): bidirectional pin "GPIO[23]" has no driver
    Warning (13040): bidirectional pin "GPIO[24]" has no driver
    Warning (13040): bidirectional pin "GPIO[25]" has no driver
    Warning (13040): bidirectional pin "GPIO[26]" has no driver
    Warning (13040): bidirectional pin "GPIO[27]" has no driver
    Warning (13040): bidirectional pin "GPIO[28]" has no driver
    Warning (13040): bidirectional pin "GPIO[29]" has no driver
    Warning (13040): bidirectional pin "GPIO[30]" has no driver
    Warning (13040): bidirectional pin "GPIO[31]" has no driver
    Warning (13040): bidirectional pin "GPIO[32]" has no driver
    Warning (13040): bidirectional pin "GPIO[33]" has no driver
    Warning (13040): bidirectional pin "GPIO[34]" has no driver
    Warning (13040): bidirectional pin "GPIO[35]" has no driver
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[3]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][3]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[2]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][2]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[1]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][1]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[0]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][0]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[11]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][11]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[10]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][10]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[9]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][9]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[8]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][8]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[15]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][15]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[14]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][14]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[13]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][13]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[12]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][12]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[7]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][7]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[6]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][6]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[5]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][5]" into an OR gate
    Warning (13047): Converted the fan-out from the tri-state buffer "SDRAM_CONTROLLER:miaRam|DRAM_DQ_reg[4]" to the node "SDRAM_CONTROLLER:miaRam|readQueue[0][4]" into an OR gate
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "DRAM_ADDR[6]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[7]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[8]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[9]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[11]" is stuck at GND
    Warning (13410): Pin "DRAM_ADDR[12]" is stuck at GND
    Warning (13410): Pin "DRAM_BA[0]" is stuck at GND
    Warning (13410): Pin "DRAM_BA[1]" is stuck at GND
    Warning (13410): Pin "DRAM_CKE" is stuck at VCC
    Warning (13410): Pin "DRAM_CS_N" is stuck at GND
    Warning (13410): Pin "HEX0[0]" is stuck at GND
    Warning (13410): Pin "HEX0[1]" is stuck at GND
    Warning (13410): Pin "HEX0[2]" is stuck at GND
    Warning (13410): Pin "HEX0[3]" is stuck at GND
    Warning (13410): Pin "HEX0[4]" is stuck at GND
    Warning (13410): Pin "HEX0[5]" is stuck at GND
    Warning (13410): Pin "HEX0[6]" is stuck at GND
    Warning (13410): Pin "HEX0[7]" is stuck at GND
    Warning (13410): Pin "HEX1[0]" is stuck at GND
    Warning (13410): Pin "HEX1[1]" is stuck at GND
    Warning (13410): Pin "HEX1[2]" is stuck at GND
    Warning (13410): Pin "HEX1[3]" is stuck at GND
    Warning (13410): Pin "HEX1[4]" is stuck at GND
    Warning (13410): Pin "HEX1[5]" is stuck at GND
    Warning (13410): Pin "HEX1[6]" is stuck at GND
    Warning (13410): Pin "HEX1[7]" is stuck at GND
    Warning (13410): Pin "HEX2[0]" is stuck at GND
    Warning (13410): Pin "HEX2[1]" is stuck at GND
    Warning (13410): Pin "HEX2[2]" is stuck at GND
    Warning (13410): Pin "HEX2[3]" is stuck at GND
    Warning (13410): Pin "HEX2[4]" is stuck at GND
    Warning (13410): Pin "HEX2[5]" is stuck at GND
    Warning (13410): Pin "HEX2[6]" is stuck at GND
    Warning (13410): Pin "HEX2[7]" is stuck at GND
    Warning (13410): Pin "HEX3[0]" is stuck at GND
    Warning (13410): Pin "HEX3[1]" is stuck at GND
    Warning (13410): Pin "HEX3[2]" is stuck at GND
    Warning (13410): Pin "HEX3[3]" is stuck at GND
    Warning (13410): Pin "HEX3[4]" is stuck at GND
    Warning (13410): Pin "HEX3[5]" is stuck at GND
    Warning (13410): Pin "HEX3[6]" is stuck at GND
    Warning (13410): Pin "HEX3[7]" is stuck at GND
    Warning (13410): Pin "HEX4[0]" is stuck at GND
    Warning (13410): Pin "HEX4[1]" is stuck at GND
    Warning (13410): Pin "HEX4[2]" is stuck at GND
    Warning (13410): Pin "HEX4[3]" is stuck at GND
    Warning (13410): Pin "HEX4[4]" is stuck at GND
    Warning (13410): Pin "HEX4[5]" is stuck at GND
    Warning (13410): Pin "HEX4[6]" is stuck at GND
    Warning (13410): Pin "HEX4[7]" is stuck at GND
    Warning (13410): Pin "HEX5[0]" is stuck at GND
    Warning (13410): Pin "HEX5[1]" is stuck at GND
    Warning (13410): Pin "HEX5[2]" is stuck at GND
    Warning (13410): Pin "HEX5[3]" is stuck at GND
    Warning (13410): Pin "HEX5[4]" is stuck at GND
    Warning (13410): Pin "HEX5[5]" is stuck at GND
    Warning (13410): Pin "HEX5[6]" is stuck at GND
    Warning (13410): Pin "HEX5[7]" is stuck at GND
    Warning (13410): Pin "LEDR[2]" is stuck at GND
    Warning (13410): Pin "LEDR[3]" is stuck at GND
    Warning (13410): Pin "LEDR[4]" is stuck at GND
    Warning (13410): Pin "LEDR[5]" is stuck at VCC
    Warning (13410): Pin "LEDR[6]" is stuck at GND
    Warning (13410): Pin "GSENSOR_CS_N" is stuck at GND
    Warning (13410): Pin "GSENSOR_SCLK" is stuck at GND
Info (286031): Timing-Driven Synthesis is running on partition "Top"
Info (17016): Found the following redundant logic cells in design
    Info (17048): Logic cell "lpm_divide:Div2|lpm_divide_vco:auto_generated|abs_divider_4dg:divider|alt_u_div_ske:divider|add_sub_11_result_int[3]~18"
    Info (17048): Logic cell "lpm_divide:Div2|lpm_divide_vco:auto_generated|abs_divider_4dg:divider|alt_u_div_ske:divider|add_sub_11_result_int[2]~20"
    Info (17048): Logic cell "lpm_divide:Div2|lpm_divide_vco:auto_generated|abs_divider_4dg:divider|alt_u_div_ske:divider|add_sub_11_result_int[1]~22"
Info (144001): Generated suppressed messages file Z:/Users/dariogogliandolo/Google Drive/Altera/projects/SDRAM_VGA/SDRAM_VGA.map.smsg
Info (35024): Successfully connected in-system debug instance "auto_signaltap_0" to all 72 required data inputs, trigger inputs, acquisition clocks, and dynamic pins
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL
Warning (15899): PLL "PLLVGA:pll1|altpll:altpll_component|PLLVGA_altpll:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
Warning (21074): Design contains 3 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "ADC_CLK_10"
    Warning (15610): No output dependent on input pin "GSENSOR_INT[1]"
    Warning (15610): No output dependent on input pin "GSENSOR_INT[2]"
Info (21057): Implemented 12504 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 20 input pins
    Info (21059): Implemented 98 output pins
    Info (21060): Implemented 71 bidirectional pins
    Info (21061): Implemented 12160 logic cells
    Info (21064): Implemented 152 RAM segments
    Info (21065): Implemented 2 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 356 warnings
    Info: Peak virtual memory: 799 megabytes
    Info: Processing ended: Tue Aug 08 17:17:49 2017
    Info: Elapsed time: 00:09:29
    Info: Total CPU time (on all processors): 00:09:49
Info: *******************************************************************
Info: Running Quartus Prime Fitter
    Info: Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
    Info: Processing started: Tue Aug 08 17:17:51 2017
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SDRAM_VGA -c SDRAM_VGA
Info: qfit2_default_script.tcl version: #1
Info: Project  = SDRAM_VGA
Info: Revision = SDRAM_VGA
Info (20030): Parallel compilation is enabled and will use 3 of the 3 processors detected
Info (119006): Selected device 10M50DAF484C7G for design "SDRAM_VGA"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (15535): Implemented PLL "pll2:test|altpll:altpll_component|pll2_altpll:auto_generated|pll1" as MAX 10 PLL type
    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll2:test|altpll:altpll_component|pll2_altpll:auto_generated|wire_pll1_clk[0] port
    Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 108 degrees (3000 ps) for pll2:test|altpll:altpll_component|pll2_altpll:auto_generated|wire_pll1_clk[1] port
Info (15535): Implemented PLL "PLLVGA:pll1|altpll:altpll_component|PLLVGA_altpll:auto_generated|pll1" as MAX 10 PLL type
    Info (15099): Implementing clock multiplication of 74, clock division of 147, and phase shift of 0 degrees (0 ps) for PLLVGA:pll1|altpll:altpll_component|PLLVGA_altpll:auto_generated|wire_pll1_clk[0] port
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info (176445): Device 10M08DAF484I7G is compatible
    Info (176445): Device 10M08DAF484I7P is compatible
    Info (176445): Device 10M16DAF484C7G is compatible
    Info (176445): Device 10M16DAF484I7G is compatible
    Info (176445): Device 10M25DAF484C7G is compatible
    Info (176445): Device 10M25DAF484I7G is compatible
    Info (176445): Device 10M50DAF484I7G is compatible
    Info (176445): Device 10M50DAF484I7P is compatible
    Info (176445): Device 10M40DAF484C7G is compatible
    Info (176445): Device 10M40DAF484I7G is compatible
Info (169124): Fitter converted 4 user pins into dedicated programming pins
    Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location H10
    Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location H9
    Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location G9
    Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location F8
Info (169141): DATA[0] dual-purpose pin not reserved
Info (12825): Data[1]/ASDO dual-purpose pin not reserved
Info (12825): nCSO dual-purpose pin not reserved
Info (12825): DCLK dual-purpose pin not reserved
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity sld_hub
        Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz
        Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Info (332104): Reading SDC File: 'SDRAM_VGA.out.sdc'
Warning (332043): Overwriting existing clock: altera_reserved_tck
Info (332104): Reading SDC File: 'SDRAM_VGA.SDC'
Warning (332043): Overwriting existing clock: ADC_CLK_10
Warning (332043): Overwriting existing clock: MAX10_CLK1_50
Warning (332043): Overwriting existing clock: MAX10_CLK2_50
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: test|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: test|altpll_component|auto_generated|pll1|clk[1]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332099):  You called derive_pll_clocks. User-defined clock found on pll: pll1|altpll_component|auto_generated|pll1|clk[0]. Original clock has priority over derived pll clocks. No clocks added to this pll.
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: altera_internal_jtag  from: tck  to: tckutap
Info (332152): The following assignments are ignored by the derive_clock_uncertainty command
Warning (332061): Virtual clock ram is never referenced in any input or output delay assignment.
Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command
    Info (332172): Setup clock transfer from MAX10_CLK1_50 (Rise) to MAX10_CLK1_50 (Rise) has uncertainty 0.020 that is less than the recommended uncertainty 0.090
    Info (332172): Hold clock transfer from MAX10_CLK1_50 (Rise) to MAX10_CLK1_50 (Rise) has uncertainty 0.020 that is less than the recommended uncertainty 0.090
    Info (332172): Setup clock transfer from MAX10_CLK1_50 (Rise) to test|altpll_component|auto_generated|pll1|clk[0] (Rise) has uncertainty 0.080 that is less than the recommended uncertainty 0.150
    Info (332172): Hold clock transfer from MAX10_CLK1_50 (Rise) to test|altpll_component|auto_generated|pll1|clk[0] (Rise) has uncertainty 0.110 that is less than the recommended uncertainty 0.150
    Info (332172): Setup clock transfer from MAX10_CLK1_50 (Fall) to test|altpll_component|auto_generated|pll1|clk[0] (Rise) has uncertainty 0.080 that is less than the recommended uncertainty 0.150
    Info (332172): Hold clock transfer from MAX10_CLK1_50 (Fall) to test|altpll_component|auto_generated|pll1|clk[0] (Rise) has uncertainty 0.110 that is less than the recommended uncertainty 0.150
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 8 clocks
    Info (332111):   Period   Clock Name
    Info (332111): ======== ============
    Info (332111):  100.000   ADC_CLK_10
    Info (332111):  100.000 altera_reserved_tck
    Info (332111):   20.000 MAX10_CLK1_50
    Info (332111):   20.000 MAX10_CLK2_50
    Info (332111):   39.729 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332111):   10.000          ram
    Info (332111):   10.000 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332111):   10.000 test|altpll_component|auto_generated|pll1|clk[1]
Info (176353): Automatically promoted node MAX10_CLK1_50~input (placed in PIN P11 (CLK7p, DIFFIO_TX_RX_B20p, DIFFOUT_B20p, High_Speed))
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[17]
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|acq_data_in_reg[17]
Info (176353): Automatically promoted node pll2:test|altpll:altpll_component|pll2_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_2)
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
Info (176353): Automatically promoted node pll2:test|altpll:altpll_component|pll2_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C1 of PLL_2)
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
Info (176353): Automatically promoted node PLLVGA:pll1|altpll:altpll_component|PLLVGA_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_1)
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18
Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
Info (176353): Automatically promoted node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all
    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]~0
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~0
        Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset
Info (176233): Starting register packing
Info (176235): Finished register packing
    Extra Info (176219): No registers were packed into other blocks
Warning (15064): PLL "pll2:test|altpll:altpll_component|pll2_altpll:auto_generated|pll1" output port clk[0] feeds output pin "LEDR[8]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning (15064): PLL "pll2:test|altpll:altpll_component|pll2_altpll:auto_generated|pll1" output port clk[1] feeds output pin "LEDR[7]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning (15064): PLL "pll2:test|altpll:altpll_component|pll2_altpll:auto_generated|pll1" output port clk[1] feeds output pin "DRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:10
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:05
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:01:02
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 9% of the available device resources
    Info (170196): Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X45_Y22 to location X55_Y32
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:01:28
Info (11888): Total time spent on timing analysis during the Fitter is 23.38 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:30
Warning (169177): 88 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info (169178): Pin ADC_CLK_10 uses I/O standard 3.3-V LVTTL at N5
    Info (169178): Pin GSENSOR_INT[1] uses I/O standard 3.3-V LVTTL at Y14
    Info (169178): Pin GSENSOR_INT[2] uses I/O standard 3.3-V LVTTL at Y13
    Info (169178): Pin GSENSOR_SDI uses I/O standard 3.3-V LVTTL at V11
    Info (169178): Pin GSENSOR_SDO uses I/O standard 3.3-V LVTTL at V12
    Info (169178): Pin ARDUINO_IO[0] uses I/O standard 3.3-V LVTTL at AB5
    Info (169178): Pin ARDUINO_IO[1] uses I/O standard 3.3-V LVTTL at AB6
    Info (169178): Pin ARDUINO_IO[2] uses I/O standard 3.3-V LVTTL at AB7
    Info (169178): Pin ARDUINO_IO[3] uses I/O standard 3.3-V LVTTL at AB8
    Info (169178): Pin ARDUINO_IO[4] uses I/O standard 3.3-V LVTTL at AB9
    Info (169178): Pin ARDUINO_IO[5] uses I/O standard 3.3-V LVTTL at Y10
    Info (169178): Pin ARDUINO_IO[6] uses I/O standard 3.3-V LVTTL at AA11
    Info (169178): Pin ARDUINO_IO[7] uses I/O standard 3.3-V LVTTL at AA12
    Info (169178): Pin ARDUINO_IO[8] uses I/O standard 3.3-V LVTTL at AB17
    Info (169178): Pin ARDUINO_IO[9] uses I/O standard 3.3-V LVTTL at AA17
    Info (169178): Pin ARDUINO_IO[10] uses I/O standard 3.3-V LVTTL at AB19
    Info (169178): Pin ARDUINO_IO[11] uses I/O standard 3.3-V LVTTL at AA19
    Info (169178): Pin ARDUINO_IO[12] uses I/O standard 3.3-V LVTTL at Y19
    Info (169178): Pin ARDUINO_IO[13] uses I/O standard 3.3-V LVTTL at AB20
    Info (169178): Pin ARDUINO_IO[14] uses I/O standard 3.3-V LVTTL at AB21
    Info (169178): Pin ARDUINO_IO[15] uses I/O standard 3.3-V LVTTL at AA20
    Info (169178): Pin ARDUINO_RESET_N uses I/O standard 3.3 V Schmitt Trigger at F16
    Info (169178): Pin GPIO[0] uses I/O standard 3.3-V LVTTL at V10
    Info (169178): Pin GPIO[1] uses I/O standard 3.3-V LVTTL at W10
    Info (169178): Pin GPIO[2] uses I/O standard 3.3-V LVTTL at V9
    Info (169178): Pin GPIO[3] uses I/O standard 3.3-V LVTTL at W9
    Info (169178): Pin GPIO[4] uses I/O standard 3.3-V LVTTL at V8
    Info (169178): Pin GPIO[5] uses I/O standard 3.3-V LVTTL at W8
    Info (169178): Pin GPIO[6] uses I/O standard 3.3-V LVTTL at V7
    Info (169178): Pin GPIO[7] uses I/O standard 3.3-V LVTTL at W7
    Info (169178): Pin GPIO[8] uses I/O standard 3.3-V LVTTL at W6
    Info (169178): Pin GPIO[9] uses I/O standard 3.3-V LVTTL at V5
    Info (169178): Pin GPIO[10] uses I/O standard 3.3-V LVTTL at W5
    Info (169178): Pin GPIO[11] uses I/O standard 3.3-V LVTTL at AA15
    Info (169178): Pin GPIO[12] uses I/O standard 3.3-V LVTTL at AA14
    Info (169178): Pin GPIO[13] uses I/O standard 3.3-V LVTTL at W13
    Info (169178): Pin GPIO[14] uses I/O standard 3.3-V LVTTL at W12
    Info (169178): Pin GPIO[15] uses I/O standard 3.3-V LVTTL at AB13
    Info (169178): Pin GPIO[16] uses I/O standard 3.3-V LVTTL at AB12
    Info (169178): Pin GPIO[17] uses I/O standard 3.3-V LVTTL at Y11
    Info (169178): Pin GPIO[18] uses I/O standard 3.3-V LVTTL at AB11
    Info (169178): Pin GPIO[19] uses I/O standard 3.3-V LVTTL at W11
    Info (169178): Pin GPIO[20] uses I/O standard 3.3-V LVTTL at AB10
    Info (169178): Pin GPIO[21] uses I/O standard 3.3-V LVTTL at AA10
    Info (169178): Pin GPIO[22] uses I/O standard 3.3-V LVTTL at AA9
    Info (169178): Pin GPIO[23] uses I/O standard 3.3-V LVTTL at Y8
    Info (169178): Pin GPIO[24] uses I/O standard 3.3-V LVTTL at AA8
    Info (169178): Pin GPIO[25] uses I/O standard 3.3-V LVTTL at Y7
    Info (169178): Pin GPIO[26] uses I/O standard 3.3-V LVTTL at AA7
    Info (169178): Pin GPIO[27] uses I/O standard 3.3-V LVTTL at Y6
    Info (169178): Pin GPIO[28] uses I/O standard 3.3-V LVTTL at AA6
    Info (169178): Pin GPIO[29] uses I/O standard 3.3-V LVTTL at Y5
    Info (169178): Pin GPIO[30] uses I/O standard 3.3-V LVTTL at AA5
    Info (169178): Pin GPIO[31] uses I/O standard 3.3-V LVTTL at Y4
    Info (169178): Pin GPIO[32] uses I/O standard 3.3-V LVTTL at AB3
    Info (169178): Pin GPIO[33] uses I/O standard 3.3-V LVTTL at Y3
    Info (169178): Pin GPIO[34] uses I/O standard 3.3-V LVTTL at AB2
    Info (169178): Pin GPIO[35] uses I/O standard 3.3-V LVTTL at AA2
    Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at Y21
    Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at Y20
    Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at AA22
    Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at AA21
    Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at Y22
    Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at W22
    Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at W20
    Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at V21
    Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at P21
    Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at J22
    Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at H21
    Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at H22
    Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at G22
    Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at G20
    Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at G19
    Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at F22
    Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at F15
    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at C10
    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at C11
    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at D12
    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at C12
    Info (169178): Pin MAX10_CLK2_50 uses I/O standard 3.3-V LVTTL at N14
    Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at A12
    Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at B12
    Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at A13
    Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at A14
    Info (169178): Pin KEY[0] uses I/O standard 3.3 V Schmitt Trigger at B8
    Info (169178): Pin MAX10_CLK1_50 uses I/O standard 3.3-V LVTTL at P11
    Info (169178): Pin KEY[1] uses I/O standard 3.3 V Schmitt Trigger at A7
    Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at B14
Warning (169064): Following 55 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
    Info (169065): Pin GSENSOR_SDI has a permanently disabled output enable
    Info (169065): Pin GSENSOR_SDO has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[0] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[1] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[2] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[3] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[4] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[5] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[6] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[7] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[8] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[9] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[10] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[11] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[12] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[13] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[14] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_IO[15] has a permanently disabled output enable
    Info (169065): Pin ARDUINO_RESET_N has a permanently disabled output enable
    Info (169065): Pin GPIO[0] has a permanently disabled output enable
    Info (169065): Pin GPIO[1] has a permanently disabled output enable
    Info (169065): Pin GPIO[2] has a permanently disabled output enable
    Info (169065): Pin GPIO[3] has a permanently disabled output enable
    Info (169065): Pin GPIO[4] has a permanently disabled output enable
    Info (169065): Pin GPIO[5] has a permanently disabled output enable
    Info (169065): Pin GPIO[6] has a permanently disabled output enable
    Info (169065): Pin GPIO[7] has a permanently disabled output enable
    Info (169065): Pin GPIO[8] has a permanently disabled output enable
    Info (169065): Pin GPIO[9] has a permanently disabled output enable
    Info (169065): Pin GPIO[10] has a permanently disabled output enable
    Info (169065): Pin GPIO[11] has a permanently disabled output enable
    Info (169065): Pin GPIO[12] has a permanently disabled output enable
    Info (169065): Pin GPIO[13] has a permanently disabled output enable
    Info (169065): Pin GPIO[14] has a permanently disabled output enable
    Info (169065): Pin GPIO[15] has a permanently disabled output enable
    Info (169065): Pin GPIO[16] has a permanently disabled output enable
    Info (169065): Pin GPIO[17] has a permanently disabled output enable
    Info (169065): Pin GPIO[18] has a permanently disabled output enable
    Info (169065): Pin GPIO[19] has a permanently disabled output enable
    Info (169065): Pin GPIO[20] has a permanently disabled output enable
    Info (169065): Pin GPIO[21] has a permanently disabled output enable
    Info (169065): Pin GPIO[22] has a permanently disabled output enable
    Info (169065): Pin GPIO[23] has a permanently disabled output enable
    Info (169065): Pin GPIO[24] has a permanently disabled output enable
    Info (169065): Pin GPIO[25] has a permanently disabled output enable
    Info (169065): Pin GPIO[26] has a permanently disabled output enable
    Info (169065): Pin GPIO[27] has a permanently disabled output enable
    Info (169065): Pin GPIO[28] has a permanently disabled output enable
    Info (169065): Pin GPIO[29] has a permanently disabled output enable
    Info (169065): Pin GPIO[30] has a permanently disabled output enable
    Info (169065): Pin GPIO[31] has a permanently disabled output enable
    Info (169065): Pin GPIO[32] has a permanently disabled output enable
    Info (169065): Pin GPIO[33] has a permanently disabled output enable
    Info (169065): Pin GPIO[34] has a permanently disabled output enable
    Info (169065): Pin GPIO[35] has a permanently disabled output enable
Info (144001): Generated suppressed messages file Z:/Users/dariogogliandolo/Google Drive/Altera/projects/SDRAM_VGA/SDRAM_VGA.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 12 warnings
    Info: Peak virtual memory: 1538 megabytes
    Info: Processing ended: Tue Aug 08 17:21:26 2017
    Info: Elapsed time: 00:03:35
    Info: Total CPU time (on all processors): 00:06:03
Info: *******************************************************************
Info: Running Quartus Prime Assembler
    Info: Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
    Info: Processing started: Tue Aug 08 17:21:27 2017
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off SDRAM_VGA -c SDRAM_VGA
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 575 megabytes
    Info: Processing ended: Tue Aug 08 17:21:33 2017
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:06
Info (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
    Info: Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
    Info: Processing started: Tue Aug 08 17:21:35 2017
Info: Command: quartus_sta SDRAM_VGA -c SDRAM_VGA
Info: qsta_default_script.tcl version: #1
Info (20030): Parallel compilation is enabled and will use 3 of the 3 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332164): Evaluating HDL-embedded SDC commands
    Info (332165): Entity sld_hub
        Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz
        Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
Info (332104): Reading SDC File: 'SDRAM_VGA.out.sdc'
Warning (332043): Overwriting existing clock: altera_reserved_tck
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: altera_internal_jtag  from: tck  to: tckutap
Warning (332061): Virtual clock ram is never referenced in any input or output delay assignment.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -164.670
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):  -164.670           -3467.055 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):  -119.611          -86782.923 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):    -1.918            -193.013 test|altpll_component|auto_generated|pll1|clk[1]
    Info (332119):    18.361               0.000 MAX10_CLK1_50
    Info (332119):    43.828               0.000 altera_reserved_tck
Info (332146): Worst-case hold slack is 0.310
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):     0.310               0.000 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     0.339               0.000 altera_reserved_tck
    Info (332119):     0.443               0.000 MAX10_CLK1_50
    Info (332119):     0.659               0.000 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     8.605               0.000 test|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case recovery slack is 94.731
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):    94.731               0.000 altera_reserved_tck
Info (332146): Worst-case removal slack is 0.902
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):     0.902               0.000 altera_reserved_tck
Info (332146): Worst-case minimum pulse width slack is 4.667
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):     4.667               0.000 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     4.713               0.000 test|altpll_component|auto_generated|pll1|clk[1]
    Info (332119):     9.649               0.000 MAX10_CLK1_50
    Info (332119):     9.838               0.000 MAX10_CLK2_50
    Info (332119):    19.608               0.000 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):    49.523               0.000 altera_reserved_tck
    Info (332119):    96.000               0.000 ADC_CLK_10
Info (332114): Report Metastability: Found 8 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 8
    Info (332114): Shortest Synchronizer Chain: 4 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 39.226 ns
    Info (332114):
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: altera_internal_jtag  from: tck  to: tckutap
Warning (332061): Virtual clock ram is never referenced in any input or output delay assignment.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -146.110
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):  -146.110           -2991.328 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):  -107.820          -78218.942 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):    -1.537            -147.656 test|altpll_component|auto_generated|pll1|clk[1]
    Info (332119):    18.516               0.000 MAX10_CLK1_50
    Info (332119):    44.249               0.000 altera_reserved_tck
Info (332146): Worst-case hold slack is 0.288
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):     0.288               0.000 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     0.305               0.000 altera_reserved_tck
    Info (332119):     0.410               0.000 MAX10_CLK1_50
    Info (332119):     0.609               0.000 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     8.488               0.000 test|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case recovery slack is 95.150
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):    95.150               0.000 altera_reserved_tck
Info (332146): Worst-case removal slack is 0.827
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):     0.827               0.000 altera_reserved_tck
Info (332146): Worst-case minimum pulse width slack is 4.682
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):     4.682               0.000 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     4.700               0.000 test|altpll_component|auto_generated|pll1|clk[1]
    Info (332119):     9.660               0.000 MAX10_CLK1_50
    Info (332119):     9.778               0.000 MAX10_CLK2_50
    Info (332119):    19.579               0.000 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):    49.540               0.000 altera_reserved_tck
    Info (332119):    96.000               0.000 ADC_CLK_10
Info (332114): Report Metastability: Found 8 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 8
    Info (332114): Shortest Synchronizer Chain: 4 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 39.962 ns
    Info (332114):
Info: Analyzing Fast 1200mV 0C Model
Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
    Info (332098): Cell: altera_internal_jtag  from: tck  to: tckutap
Warning (332061): Virtual clock ram is never referenced in any input or output delay assignment.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -45.565
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):   -45.565            -460.227 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):   -43.606          -31480.785 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     0.692               0.000 test|altpll_component|auto_generated|pll1|clk[1]
    Info (332119):    19.271               0.000 MAX10_CLK1_50
    Info (332119):    47.523               0.000 altera_reserved_tck
Info (332146): Worst-case hold slack is 0.125
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):     0.125               0.000 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     0.147               0.000 altera_reserved_tck
    Info (332119):     0.171               0.000 MAX10_CLK1_50
    Info (332119):     0.256               0.000 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     7.630               0.000 test|altpll_component|auto_generated|pll1|clk[1]
Info (332146): Worst-case recovery slack is 97.350
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):    97.350               0.000 altera_reserved_tck
Info (332146): Worst-case removal slack is 0.403
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):     0.403               0.000 altera_reserved_tck
Info (332146): Worst-case minimum pulse width slack is 4.711
    Info (332119):     Slack       End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):     4.711               0.000 test|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):     4.754               0.000 test|altpll_component|auto_generated|pll1|clk[1]
    Info (332119):     9.328               0.000 MAX10_CLK1_50
    Info (332119):     9.532               0.000 MAX10_CLK2_50
    Info (332119):    19.598               0.000 pll1|altpll_component|auto_generated|pll1|clk[0]
    Info (332119):    49.386               0.000 altera_reserved_tck
    Info (332119):    96.000               0.000 ADC_CLK_10
Info (332114): Report Metastability: Found 8 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 8
    Info (332114): Shortest Synchronizer Chain: 4 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 44.808 ns
    Info (332114):
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
    Info: Peak virtual memory: 779 megabytes
    Info: Processing ended: Tue Aug 08 17:21:52 2017
    Info: Elapsed time: 00:00:17
    Info: Total CPU time (on all processors): 00:00:32
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
    Info: Processing started: Tue Aug 08 17:21:53 2017
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off SDRAM_VGA -c SDRAM_VGA
Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
Info (204019): Generated file SDRAM_VGA.vo in folder "Z:/Users/dariogogliandolo/Google Drive/Altera/projects/SDRAM_VGA/simulation/modelsim/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 644 megabytes
    Info: Processing ended: Tue Aug 08 17:22:00 2017
    Info: Elapsed time: 00:00:07
    Info: Total CPU time (on all processors): 00:00:07
Info (293000): Quartus Prime Full Compilation was successful. 0 errors, 376 warnings