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  1.  
  2.         Intel(R) Pentium(R) M processor 2.13GHz
  3. x86 Family 6 Model 13 Stepping 8, GenuineIntel
  4. Microcode signature: 00000020
  5. HTT         -   Hyperthreading enabled
  6. HYPERVISOR  -   Hypervisor is present
  7. VMX         -   Supports Intel hardware-assisted virtualization
  8. SVM         -   Supports AMD hardware-assisted virtualization
  9. X64         -   Supports 64-bit mode
  10.  
  11. SMX         -   Supports Intel trusted execution
  12. SKINIT      -   Supports AMD SKINIT
  13.  
  14. NX          -   Supports no-execute page protection
  15. SMEP        *   Supports Supervisor Mode Execution Prevention
  16. SMAP        -   Supports Supervisor Mode Access Prevention
  17. PAGE1GB     -   Supports 1 GB large pages
  18. PAE         *   Supports > 32-bit physical addresses
  19. PAT         *   Supports Page Attribute Table
  20. PSE         *   Supports 4 MB pages
  21. PSE36       -   Supports > 32-bit address 4 MB pages
  22. PGE         *   Supports global bit in page tables
  23. SS          *   Supports bus snooping for cache operations
  24. VME         *   Supports Virtual-8086 mode
  25. RDWRFSGSBASE    -   Supports direct GS/FS base access
  26.  
  27. FPU         *   Implements i387 floating point instructions
  28. MMX         *   Supports MMX instruction set
  29. MMXEXT      -   Implements AMD MMX extensions
  30. 3DNOW       -   Supports 3DNow! instructions
  31. 3DNOWEXT    -   Supports 3DNow! extension instructions
  32. SSE         *   Supports Streaming SIMD Extensions
  33. SSE2        *   Supports Streaming SIMD Extensions 2
  34. SSE3        -   Supports Streaming SIMD Extensions 3
  35. SSSE3       -   Supports Supplemental SIMD Extensions 3
  36. SSE4a       -   Supports Streaming SIMDR Extensions 4a
  37. SSE4.1      -   Supports Streaming SIMD Extensions 4.1
  38. SSE4.2      -   Supports Streaming SIMD Extensions 4.2
  39.  
  40. AES         -   Supports AES extensions
  41. AVX         -   Supports AVX intruction extensions
  42. FMA         -   Supports FMA extensions using YMM state
  43. MSR         *   Implements RDMSR/WRMSR instructions
  44. MTRR        *   Supports Memory Type Range Registers
  45. XSAVE       -   Supports XSAVE/XRSTOR instructions
  46. OSXSAVE     -   Supports XSETBV/XGETBV instructions
  47. RDRAND      -   Supports RDRAND instruction
  48. RDSEED      -   Supports RDSEED instruction
  49.  
  50. CMOV        *   Supports CMOVcc instruction
  51. CLFSH       *   Supports CLFLUSH instruction
  52. CX8         *   Supports compare and exchange 8-byte instructions
  53. CX16        -   Supports CMPXCHG16B instruction
  54. BMI1        -   Supports bit manipulation extensions 1
  55. BMI2        -   Supports bit manipulation extensions 2
  56. ADX         -   Supports ADCX/ADOX instructions
  57. DCA         -   Supports prefetch from memory-mapped device
  58. F16C        -   Supports half-precision instruction
  59. FXSR        *   Supports FXSAVE/FXSTOR instructions
  60. FFXSR       -   Supports optimized FXSAVE/FSRSTOR instruction
  61. MONITOR     -   Supports MONITOR and MWAIT instructions
  62. MOVBE       -   Supports MOVBE instruction
  63. ERMSB       -   Supports Enhanced REP MOVSB/STOSB
  64. PCLMULDQ    -   Supports PCLMULDQ instruction
  65. POPCNT      -   Supports POPCNT instruction
  66. LZCNT       -   Supports LZCNT instruction
  67. SEP         *   Supports fast system call instructions
  68. LAHF-SAHF   -   Supports LAHF/SAHF instructions in 64-bit mode
  69. HLE         *   Supports Hardware Lock Elision instructions
  70. RTM         -   Supports Restricted Transactional Memory instructions
  71.  
  72. DE          *   Supports I/O breakpoints including CR4.DE
  73. DTES64      -   Can write history of 64-bit branch addresses
  74. DS          *   Implements memory-resident debug buffer
  75. DS-CPL      -   Supports Debug Store feature with CPL
  76. PCID        -   Supports PCIDs and settable CR4.PCIDE
  77. INVPCID     -   Supports INVPCID instruction
  78. PDCM        -   Supports Performance Capabilities MSR
  79. RDTSCP      -   Supports RDTSCP instruction
  80. TSC         *   Supports RDTSC instruction
  81. TSC-DEADLINE    -   Local APIC supports one-shot deadline timer
  82. TSC-INVARIANT   -   TSC runs at constant rate
  83. xTPR        -   Supports disabling task priority messages
  84.  
  85. EIST        *   Supports Enhanced Intel Speedstep
  86. ACPI        *   Implements MSR for power management
  87. TM          *   Implements thermal monitor circuitry
  88. TM2         *   Implements Thermal Monitor 2 control
  89. APIC        -   Implements software-accessible local APIC
  90. x2APIC      -   Supports x2APIC
  91.  
  92. CNXT-ID     -   L1 data cache mode adaptive or BIOS
  93.  
  94. MCE         *   Supports Machine Check, INT18 and CR4.MCE
  95. MCA         *   Implements Machine Check Architecture
  96. PBE         *   Supports use of FERR#/PBE# pin
  97.  
  98. PSN         -   Implements 96-bit processor serial number
  99.  
  100. PREFETCHW   -   Supports PREFETCHW instruction
  101.  
  102. Maximum implemented CPUID leaves: 00000002 (Basic), 80000008 (Extended).
  103.  
  104. Logical to Physical Processor Map:
  105. *  Physical Processor 0
  106.  
  107. Logical Processor to Socket Map:
  108. *  Socket 0
  109.  
  110. Logical Processor to NUMA Node Map:
  111. *  NUMA Node 0
  112.  
  113. Logical Processor to Cache Map:
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