API tools faq
paste
Advertisement
hanni76

Untitled

hanni76
Apr 13th, 2018
256
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 36.75 KB | None | 0 0
raw download clone embed print report
  1. /*
  2. * Copyright 2013 Maxime Ripard
  3. *
  4. * Maxime Ripard <maxime.ripard@free-electrons.com>
  5. *
  6. * This file is dual-licensed: you can use it either under the terms
  7. * of the GPL or the X11 license, at your option. Note that this dual
  8. * licensing only applies to this file, and not this project as a
  9. * whole.
  10. *
  11. * a) This file is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of the
  14. * License, or (at your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * Or, alternatively,
  22. *
  23. * b) Permission is hereby granted, free of charge, to any person
  24. * obtaining a copy of this software and associated documentation
  25. * files (the "Software"), to deal in the Software without
  26. * restriction, including without limitation the rights to use,
  27. * copy, modify, merge, publish, distribute, sublicense, and/or
  28. * sell copies of the Software, and to permit persons to whom the
  29. * Software is furnished to do so, subject to the following
  30. * conditions:
  31. *
  32. * The above copyright notice and this permission notice shall be
  33. * included in all copies or substantial portions of the Software.
  34. *
  35. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42. * OTHER DEALINGS IN THE SOFTWARE.
  43. */
  44.  
  45. #include "skeleton.dtsi"
  46.  
  47. #include <dt-bindings/interrupt-controller/arm-gic.h>
  48. #include <dt-bindings/thermal/thermal.h>
  49.  
  50. #include <dt-bindings/clock/sun6i-a31-ccu.h>
  51. #include <dt-bindings/reset/sun6i-a31-ccu.h>
  52.  
  53. / {
  54. interrupt-parent = <&gic>;
  55.  
  56. aliases {
  57. ethernet0 = &gmac;
  58. };
  59.  
  60. chosen {
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. ranges;
  64.  
  65. simplefb_hdmi: framebuffer@0 {
  66. compatible = "allwinner,simple-framebuffer",
  67. "simple-framebuffer";
  68. allwinner,pipeline = "de_be0-lcd0-hdmi";
  69. clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  70. <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
  71. <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
  72. <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
  73. status = "disabled";
  74. };
  75.  
  76. simplefb_lcd: framebuffer@1 {
  77. compatible = "allwinner,simple-framebuffer",
  78. "simple-framebuffer";
  79. allwinner,pipeline = "de_be0-lcd0";
  80. clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
  81. <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
  82. <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
  83. status = "disabled";
  84. };
  85. };
  86.  
  87. timer {
  88. compatible = "arm,armv7-timer";
  89. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  93. clock-frequency = <24000000>;
  94. arm,cpu-registers-not-fw-configured;
  95. };
  96.  
  97. cpus {
  98. enable-method = "allwinner,sun6i-a31";
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101.  
  102. cpu0: cpu@0 {
  103. compatible = "arm,cortex-a7";
  104. device_type = "cpu";
  105. reg = <0>;
  106. clocks = <&ccu CLK_CPU>;
  107. operating-points-v2 = <&cpu0_opp_table>;
  108. #cooling-cells = <2>;
  109. cooling-min-level = <0>;
  110. cooling-max-level = <3>;
  111. };
  112.  
  113. cpu@1 {
  114. compatible = "arm,cortex-a7";
  115. device_type = "cpu";
  116. reg = <1>;
  117. operating-points-v2 = <&cpu0_opp_table>;
  118. };
  119.  
  120. cpu@2 {
  121. compatible = "arm,cortex-a7";
  122. device_type = "cpu";
  123. reg = <2>;
  124. operating-points-v2 = <&cpu0_opp_table>;
  125. };
  126.  
  127. cpu@3 {
  128. compatible = "arm,cortex-a7";
  129. device_type = "cpu";
  130. reg = <3>;
  131. operating-points-v2 = <&cpu0_opp_table>;
  132. };
  133. };
  134.  
  135. cpu0_opp_table: opp_table0 {
  136. compatible = "operating-points-v2";
  137. opp-shared;
  138.  
  139. opp-1008000000 {
  140. opp-hz = /bits/ 64 <1008000000>;
  141. opp-microvolt = <1260000>;
  142. clock-latency-ns = <244144>; /* 8 32k periods */
  143. };
  144.  
  145. opp-864000000 {
  146. opp-hz = /bits/ 64 <864000000>;
  147. opp-microvolt = <1200000>;
  148. clock-latency-ns = <244144>; /* 8 32k periods */
  149. status = "disabled";
  150. };
  151.  
  152. opp-720000000 {
  153. opp-hz = /bits/ 64 <720000000>;
  154. opp-microvolt = <1100000>;
  155. clock-latency-ns = <244144>; /* 8 32k periods */
  156. status = "disabled";
  157. };
  158.  
  159. opp-480000000 {
  160. opp-hz = /bits/ 64 <480000000>;
  161. opp-microvolt = <1000000>;
  162. clock-latency-ns = <244144>; /* 8 32k periods */
  163. status = "disabled";
  164. };
  165. };
  166.  
  167. thermal-zones {
  168. cpu_thermal {
  169. /* milliseconds */
  170. polling-delay-passive = <250>;
  171. polling-delay = <1000>;
  172. thermal-sensors = <&rtp>;
  173.  
  174. cooling-maps {
  175. map0 {
  176. trip = <&cpu_alert0>;
  177. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  178. };
  179. };
  180.  
  181. trips {
  182. cpu_alert0: cpu_alert0 {
  183. /* milliCelsius */
  184. temperature = <70000>;
  185. hysteresis = <2000>;
  186. type = "passive";
  187. };
  188.  
  189. cpu_hot: cpu_hot {
  190. /* milliCelsius */
  191. temperature = <85000>;
  192. hysteresis = <2000>;
  193. type = "hot";
  194. };
  195.  
  196. cpu_crit: cpu_crit {
  197. /* milliCelsius */
  198. temperature = <100000>;
  199. hysteresis = <2000>;
  200. type = "critical";
  201. };
  202. };
  203. };
  204. };
  205.  
  206. memory {
  207. reg = <0x40000000 0x80000000>;
  208. };
  209.  
  210. pmu {
  211. compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
  212. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  213. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  214. <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  215. <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
  216. };
  217.  
  218. clocks {
  219. #address-cells = <1>;
  220. #size-cells = <1>;
  221. ranges;
  222.  
  223. osc24M: osc24M {
  224. #clock-cells = <0>;
  225. compatible = "fixed-clock";
  226. clock-frequency = <24000000>;
  227. };
  228.  
  229. osc32k: clk@0 {
  230. #clock-cells = <0>;
  231. compatible = "fixed-clock";
  232. clock-frequency = <32768>;
  233. clock-output-names = "osc32k";
  234. };
  235.  
  236. /*
  237. * The following two are dummy clocks, placeholders
  238. * used in the gmac_tx clock. The gmac driver will
  239. * choose one parent depending on the PHY interface
  240. * mode, using clk_set_rate auto-reparenting.
  241. *
  242. * The actual TX clock rate is not controlled by the
  243. * gmac_tx clock.
  244. */
  245. mii_phy_tx_clk: clk@1 {
  246. #clock-cells = <0>;
  247. compatible = "fixed-clock";
  248. clock-frequency = <25000000>;
  249. clock-output-names = "mii_phy_tx";
  250. };
  251.  
  252. gmac_int_tx_clk: clk@2 {
  253. #clock-cells = <0>;
  254. compatible = "fixed-clock";
  255. clock-frequency = <125000000>;
  256. clock-output-names = "gmac_int_tx";
  257. };
  258.  
  259. gmac_tx_clk: clk@1c200d0 {
  260. #clock-cells = <0>;
  261. compatible = "allwinner,sun7i-a20-gmac-clk";
  262. reg = <0x01c200d0 0x4>;
  263. clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
  264. clock-output-names = "gmac_tx";
  265. };
  266. };
  267.  
  268. de: display-engine {
  269. compatible = "allwinner,sun6i-a31-display-engine";
  270. allwinner,pipelines = <&fe0>, <&fe1>;
  271. status = "disabled";
  272. };
  273.  
  274. soc@1c00000 {
  275. compatible = "simple-bus";
  276. #address-cells = <1>;
  277. #size-cells = <1>;
  278. ranges;
  279.  
  280. dma: dma-controller@1c02000 {
  281. compatible = "allwinner,sun6i-a31-dma";
  282. reg = <0x01c02000 0x1000>;
  283. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  284. clocks = <&ccu CLK_AHB1_DMA>;
  285. resets = <&ccu RST_AHB1_DMA>;
  286. #dma-cells = <1>;
  287. };
  288.  
  289. tcon0: lcd-controller@1c0c000 {
  290. compatible = "allwinner,sun6i-a31-tcon";
  291. reg = <0x01c0c000 0x1000>;
  292. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  293. resets = <&ccu RST_AHB1_LCD0>;
  294. reset-names = "lcd";
  295. clocks = <&ccu CLK_AHB1_LCD0>,
  296. <&ccu CLK_LCD0_CH0>,
  297. <&ccu CLK_LCD0_CH1>;
  298. clock-names = "ahb",
  299. "tcon-ch0",
  300. "tcon-ch1";
  301. clock-output-names = "tcon0-pixel-clock";
  302.  
  303. ports {
  304. #address-cells = <1>;
  305. #size-cells = <0>;
  306.  
  307. tcon0_in: port@0 {
  308. #address-cells = <1>;
  309. #size-cells = <0>;
  310. reg = <0>;
  311.  
  312. tcon0_in_drc0: endpoint@0 {
  313. reg = <0>;
  314. remote-endpoint = <&drc0_out_tcon0>;
  315. };
  316.  
  317. tcon0_in_drc1: endpoint@1 {
  318. reg = <1>;
  319. remote-endpoint = <&drc1_out_tcon0>;
  320. };
  321. };
  322.  
  323. tcon0_out: port@1 {
  324. #address-cells = <1>;
  325. #size-cells = <0>;
  326. reg = <1>;
  327.  
  328. tcon0_out_hdmi: endpoint@1 {
  329. reg = <1>;
  330. remote-endpoint = <&hdmi_in_tcon0>;
  331. allwinner,tcon-channel = <1>;
  332. };
  333. };
  334. };
  335. };
  336.  
  337. tcon1: lcd-controller@1c0d000 {
  338. compatible = "allwinner,sun6i-a31-tcon";
  339. reg = <0x01c0d000 0x1000>;
  340. interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  341. resets = <&ccu RST_AHB1_LCD1>;
  342. reset-names = "lcd";
  343. clocks = <&ccu CLK_AHB1_LCD1>,
  344. <&ccu CLK_LCD1_CH0>,
  345. <&ccu CLK_LCD1_CH1>;
  346. clock-names = "ahb",
  347. "tcon-ch0",
  348. "tcon-ch1";
  349. clock-output-names = "tcon1-pixel-clock";
  350.  
  351. ports {
  352. #address-cells = <1>;
  353. #size-cells = <0>;
  354.  
  355. tcon1_in: port@0 {
  356. #address-cells = <1>;
  357. #size-cells = <0>;
  358. reg = <0>;
  359.  
  360. tcon1_in_drc0: endpoint@0 {
  361. reg = <0>;
  362. remote-endpoint = <&drc0_out_tcon1>;
  363. };
  364.  
  365. tcon1_in_drc1: endpoint@1 {
  366. reg = <1>;
  367. remote-endpoint = <&drc1_out_tcon1>;
  368. };
  369. };
  370.  
  371. tcon1_out: port@1 {
  372. #address-cells = <1>;
  373. #size-cells = <0>;
  374. reg = <1>;
  375.  
  376. tcon1_out_hdmi: endpoint@1 {
  377. reg = <1>;
  378. remote-endpoint = <&hdmi_in_tcon1>;
  379. allwinner,tcon-channel = <1>;
  380. };
  381. };
  382. };
  383. };
  384.  
  385. mmc0: mmc@1c0f000 {
  386. compatible = "allwinner,sun7i-a20-mmc";
  387. reg = <0x01c0f000 0x1000>;
  388. clocks = <&ccu CLK_AHB1_MMC0>,
  389. <&ccu CLK_MMC0>,
  390. <&ccu CLK_MMC0_OUTPUT>,
  391. <&ccu CLK_MMC0_SAMPLE>;
  392. clock-names = "ahb",
  393. "mmc",
  394. "output",
  395. "sample";
  396. resets = <&ccu RST_AHB1_MMC0>;
  397. reset-names = "ahb";
  398. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  399. status = "disabled";
  400. #address-cells = <1>;
  401. #size-cells = <0>;
  402. };
  403.  
  404. mmc1: mmc@1c10000 {
  405. compatible = "allwinner,sun7i-a20-mmc";
  406. reg = <0x01c10000 0x1000>;
  407. clocks = <&ccu CLK_AHB1_MMC1>,
  408. <&ccu CLK_MMC1>,
  409. <&ccu CLK_MMC1_OUTPUT>,
  410. <&ccu CLK_MMC1_SAMPLE>;
  411. clock-names = "ahb",
  412. "mmc",
  413. "output",
  414. "sample";
  415. resets = <&ccu RST_AHB1_MMC1>;
  416. reset-names = "ahb";
  417. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  418. status = "disabled";
  419. #address-cells = <1>;
  420. #size-cells = <0>;
  421. };
  422.  
  423. mmc2: mmc@1c11000 {
  424. compatible = "allwinner,sun7i-a20-mmc";
  425. reg = <0x01c11000 0x1000>;
  426. clocks = <&ccu CLK_AHB1_MMC2>,
  427. <&ccu CLK_MMC2>,
  428. <&ccu CLK_MMC2_OUTPUT>,
  429. <&ccu CLK_MMC2_SAMPLE>;
  430. clock-names = "ahb",
  431. "mmc",
  432. "output",
  433. "sample";
  434. resets = <&ccu RST_AHB1_MMC2>;
  435. reset-names = "ahb";
  436. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  437. status = "disabled";
  438. #address-cells = <1>;
  439. #size-cells = <0>;
  440. };
  441.  
  442. mmc3: mmc@1c12000 {
  443. compatible = "allwinner,sun7i-a20-mmc";
  444. reg = <0x01c12000 0x1000>;
  445. clocks = <&ccu CLK_AHB1_MMC3>,
  446. <&ccu CLK_MMC3>,
  447. <&ccu CLK_MMC3_OUTPUT>,
  448. <&ccu CLK_MMC3_SAMPLE>;
  449. clock-names = "ahb",
  450. "mmc",
  451. "output",
  452. "sample";
  453. resets = <&ccu RST_AHB1_MMC3>;
  454. reset-names = "ahb";
  455. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  456. status = "disabled";
  457. #address-cells = <1>;
  458. #size-cells = <0>;
  459. };
  460.  
  461. hdmi: hdmi@1c16000 {
  462. compatible = "allwinner,sun6i-a31-hdmi";
  463. reg = <0x01c16000 0x1000>;
  464. interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
  465. clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
  466. <&ccu CLK_HDMI_DDC>,
  467. <&ccu CLK_PLL_VIDEO0_2X>,
  468. <&ccu CLK_PLL_VIDEO1_2X>;
  469. clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
  470. resets = <&ccu RST_AHB1_HDMI>;
  471. reset-names = "ahb";
  472. dma-names = "ddc-tx", "ddc-rx", "audio-tx";
  473. dmas = <&dma 13>, <&dma 13>, <&dma 14>;
  474. status = "disabled";
  475.  
  476. ports {
  477. #address-cells = <1>;
  478. #size-cells = <0>;
  479.  
  480. hdmi_in: port@0 {
  481. #address-cells = <1>;
  482. #size-cells = <0>;
  483. reg = <0>;
  484.  
  485. hdmi_in_tcon0: endpoint@0 {
  486. reg = <0>;
  487. remote-endpoint = <&tcon0_out_hdmi>;
  488. };
  489.  
  490. hdmi_in_tcon1: endpoint@1 {
  491. reg = <1>;
  492. remote-endpoint = <&tcon1_out_hdmi>;
  493. };
  494. };
  495.  
  496. hdmi_out: port@1 {
  497. #address-cells = <1>;
  498. #size-cells = <0>;
  499. reg = <1>;
  500. };
  501. };
  502. };
  503.  
  504. usb_otg: usb@1c19000 {
  505. compatible = "allwinner,sun6i-a31-musb";
  506. reg = <0x01c19000 0x0400>;
  507. clocks = <&ccu CLK_AHB1_OTG>;
  508. resets = <&ccu RST_AHB1_OTG>;
  509. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  510. interrupt-names = "mc";
  511. phys = <&usbphy 0>;
  512. phy-names = "usb";
  513. extcon = <&usbphy 0>;
  514. status = "disabled";
  515. };
  516.  
  517. usbphy: phy@1c19400 {
  518. compatible = "allwinner,sun6i-a31-usb-phy";
  519. reg = <0x01c19400 0x10>,
  520. <0x01c1a800 0x4>,
  521. <0x01c1b800 0x4>;
  522. reg-names = "phy_ctrl",
  523. "pmu1",
  524. "pmu2";
  525. clocks = <&ccu CLK_USB_PHY0>,
  526. <&ccu CLK_USB_PHY1>,
  527. <&ccu CLK_USB_PHY2>;
  528. clock-names = "usb0_phy",
  529. "usb1_phy",
  530. "usb2_phy";
  531. resets = <&ccu RST_USB_PHY0>,
  532. <&ccu RST_USB_PHY1>,
  533. <&ccu RST_USB_PHY2>;
  534. reset-names = "usb0_reset",
  535. "usb1_reset",
  536. "usb2_reset";
  537. status = "disabled";
  538. #phy-cells = <1>;
  539. };
  540.  
  541. ehci0: usb@1c1a000 {
  542. compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
  543. reg = <0x01c1a000 0x100>;
  544. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  545. clocks = <&ccu CLK_AHB1_EHCI0>;
  546. resets = <&ccu RST_AHB1_EHCI0>;
  547. phys = <&usbphy 1>;
  548. phy-names = "usb";
  549. status = "disabled";
  550. };
  551.  
  552. ohci0: usb@1c1a400 {
  553. compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
  554. reg = <0x01c1a400 0x100>;
  555. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  556. clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
  557. resets = <&ccu RST_AHB1_OHCI0>;
  558. phys = <&usbphy 1>;
  559. phy-names = "usb";
  560. status = "disabled";
  561. };
  562.  
  563. ehci1: usb@1c1b000 {
  564. compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
  565. reg = <0x01c1b000 0x100>;
  566. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  567. clocks = <&ccu CLK_AHB1_EHCI1>;
  568. resets = <&ccu RST_AHB1_EHCI1>;
  569. phys = <&usbphy 2>;
  570. phy-names = "usb";
  571. status = "disabled";
  572. };
  573.  
  574. ohci1: usb@1c1b400 {
  575. compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
  576. reg = <0x01c1b400 0x100>;
  577. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  578. clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
  579. resets = <&ccu RST_AHB1_OHCI1>;
  580. phys = <&usbphy 2>;
  581. phy-names = "usb";
  582. status = "disabled";
  583. };
  584.  
  585. ohci2: usb@1c1c400 {
  586. compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
  587. reg = <0x01c1c400 0x100>;
  588. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  589. clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
  590. resets = <&ccu RST_AHB1_OHCI2>;
  591. status = "disabled";
  592. };
  593.  
  594. ccu: clock@1c20000 {
  595. compatible = "allwinner,sun6i-a31-ccu";
  596. reg = <0x01c20000 0x400>;
  597. clocks = <&osc24M>, <&osc32k>;
  598. clock-names = "hosc", "losc";
  599. #clock-cells = <1>;
  600. #reset-cells = <1>;
  601. };
  602.  
  603. pio: pinctrl@1c20800 {
  604. compatible = "allwinner,sun6i-a31-pinctrl";
  605. reg = <0x01c20800 0x400>;
  606. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  607. <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  608. <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  609. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  610. clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
  611. clock-names = "apb", "hosc", "losc";
  612. gpio-controller;
  613. interrupt-controller;
  614. #interrupt-cells = <3>;
  615. #gpio-cells = <3>;
  616.  
  617. gmac_pins_gmii_a: gmac_gmii@0 {
  618. pins = "PA0", "PA1", "PA2", "PA3",
  619. "PA4", "PA5", "PA6", "PA7",
  620. "PA8", "PA9", "PA10", "PA11",
  621. "PA12", "PA13", "PA14", "PA15",
  622. "PA16", "PA17", "PA18", "PA19",
  623. "PA20", "PA21", "PA22", "PA23",
  624. "PA24", "PA25", "PA26", "PA27";
  625. function = "gmac";
  626. /*
  627. * data lines in GMII mode run at 125MHz and
  628. * might need a higher signal drive strength
  629. */
  630. drive-strength = <30>;
  631. };
  632.  
  633. gmac_pins_mii_a: gmac_mii@0 {
  634. pins = "PA0", "PA1", "PA2", "PA3",
  635. "PA8", "PA9", "PA11",
  636. "PA12", "PA13", "PA14", "PA19",
  637. "PA20", "PA21", "PA22", "PA23",
  638. "PA24", "PA26", "PA27";
  639. function = "gmac";
  640. };
  641.  
  642. gmac_pins_rgmii_a: gmac_rgmii@0 {
  643. pins = "PA0", "PA1", "PA2", "PA3",
  644. "PA9", "PA10", "PA11",
  645. "PA12", "PA13", "PA14", "PA19",
  646. "PA20", "PA25", "PA26", "PA27";
  647. function = "gmac";
  648. /*
  649. * data lines in RGMII mode use DDR mode
  650. * and need a higher signal drive strength
  651. */
  652. drive-strength = <40>;
  653. };
  654.  
  655. i2c0_pins_a: i2c0@0 {
  656. pins = "PH14", "PH15";
  657. function = "i2c0";
  658. };
  659.  
  660. i2c1_pins_a: i2c1@0 {
  661. pins = "PH16", "PH17";
  662. function = "i2c1";
  663. };
  664.  
  665. i2c2_pins_a: i2c2@0 {
  666. pins = "PH18", "PH19";
  667. function = "i2c2";
  668. };
  669.  
  670. lcd0_rgb888_pins: lcd0_rgb888 {
  671. pins = "PD0", "PD1", "PD2", "PD3",
  672. "PD4", "PD5", "PD6", "PD7",
  673. "PD8", "PD9", "PD10", "PD11",
  674. "PD12", "PD13", "PD14", "PD15",
  675. "PD16", "PD17", "PD18", "PD19",
  676. "PD20", "PD21", "PD22", "PD23",
  677. "PD24", "PD25", "PD26", "PD27";
  678. function = "lcd0";
  679. };
  680.  
  681. mmc0_pins_a: mmc0@0 {
  682. pins = "PF0", "PF1", "PF2",
  683. "PF3", "PF4", "PF5";
  684. function = "mmc0";
  685. drive-strength = <30>;
  686. bias-pull-up;
  687. };
  688.  
  689. mmc1_pins_a: mmc1@0 {
  690. pins = "PG0", "PG1", "PG2", "PG3",
  691. "PG4", "PG5";
  692. function = "mmc1";
  693. drive-strength = <30>;
  694. bias-pull-up;
  695. };
  696.  
  697. mmc2_pins_a: mmc2@0 {
  698. pins = "PC6", "PC7", "PC8", "PC9",
  699. "PC10", "PC11";
  700. function = "mmc2";
  701. drive-strength = <30>;
  702. bias-pull-up;
  703. };
  704.  
  705. mmc2_8bit_emmc_pins: mmc2@1 {
  706. pins = "PC6", "PC7", "PC8", "PC9",
  707. "PC10", "PC11", "PC12",
  708. "PC13", "PC14", "PC15",
  709. "PC24";
  710. function = "mmc2";
  711. drive-strength = <30>;
  712. bias-pull-up;
  713. };
  714.  
  715. mmc3_8bit_emmc_pins: mmc3@1 {
  716. pins = "PC6", "PC7", "PC8", "PC9",
  717. "PC10", "PC11", "PC12",
  718. "PC13", "PC14", "PC15",
  719. "PC24";
  720. function = "mmc3";
  721. drive-strength = <40>;
  722. bias-pull-up;
  723. };
  724.  
  725. spi1_pins_a: spi1@0 {
  726. pins = "PG15", "PG16", "PG14", "PG13";
  727. function = "spi1";
  728. };
  729.  
  730. spi2_pins_a: spi2@0 {
  731. pins = "PH11", "PH12", "PH10", "PH9";
  732. function = "spi2";
  733. };
  734.  
  735. pwm0_pins: pwm@0 {
  736. pins = "PH13";
  737. function = "pwm0";
  738. };
  739.  
  740. pwm1_pins: pwm@1 {
  741. pins = "PH9", "PH10";
  742. function = "pwm1";
  743. };
  744.  
  745. pwm2_pins: pwm@2 {
  746. pins = "PH11", "PH12";
  747. function = "pwm2";
  748. };
  749.  
  750. pwm3_pins: pwm@3 {
  751. pins = "PA19", "PA20";
  752. function = "pwm3";
  753. };
  754.  
  755. spdif_pins_a: spdif@0 {
  756. pins = "PH28";
  757. function = "spdif";
  758. };
  759.  
  760. uart0_pins_a: uart0@0 {
  761. pins = "PH20", "PH21";
  762. function = "uart0";
  763. };
  764. };
  765.  
  766. timer@1c20c00 {
  767. compatible = "allwinner,sun4i-a10-timer";
  768. reg = <0x01c20c00 0xa0>;
  769. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  770. <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  771. <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
  772. <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  773. <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  774. clocks = <&osc24M>;
  775. };
  776.  
  777. wdt1: watchdog@1c20ca0 {
  778. compatible = "allwinner,sun6i-a31-wdt";
  779. reg = <0x01c20ca0 0x20>;
  780. };
  781.  
  782. spdif: spdif@1c21000 {
  783. #sound-dai-cells = <0>;
  784. compatible = "allwinner,sun6i-a31-spdif";
  785. reg = <0x01c21000 0x400>;
  786. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  787. clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
  788. resets = <&ccu RST_APB1_SPDIF>;
  789. clock-names = "apb", "spdif";
  790. dmas = <&dma 2>, <&dma 2>;
  791. dma-names = "rx", "tx";
  792. status = "disabled";
  793. };
  794.  
  795. i2s0: i2s@1c22000 {
  796. #sound-dai-cells = <0>;
  797. compatible = "allwinner,sun6i-a31-i2s";
  798. reg = <0x01c22000 0x400>;
  799. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  800. clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
  801. resets = <&ccu RST_APB1_DAUDIO0>;
  802. clock-names = "apb", "mod";
  803. dmas = <&dma 3>, <&dma 3>;
  804. dma-names = "rx", "tx";
  805. status = "disabled";
  806. };
  807.  
  808. i2s1: i2s@1c22400 {
  809. #sound-dai-cells = <0>;
  810. compatible = "allwinner,sun6i-a31-i2s";
  811. reg = <0x01c22400 0x400>;
  812. interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  813. clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
  814. resets = <&ccu RST_APB1_DAUDIO1>;
  815. clock-names = "apb", "mod";
  816. dmas = <&dma 4>, <&dma 4>;
  817. dma-names = "rx", "tx";
  818. status = "disabled";
  819. };
  820.  
  821. lradc: lradc@1c22800 {
  822. compatible = "allwinner,sun4i-a10-lradc-keys";
  823. reg = <0x01c22800 0x100>;
  824. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  825. status = "disabled";
  826. };
  827.  
  828. pwm: pwm@01c21400 {
  829. compatible = "allwinner,sun6i-a31-pwm";
  830. reg = <0x01c21400 0x40>;
  831. clocks = <&osc24M>;
  832. #pwm-cells = <3>;
  833. status = "disabled";
  834. };
  835.  
  836. rtp: rtp@1c25000 {
  837. compatible = "allwinner,sun6i-a31-ts";
  838. reg = <0x01c25000 0x100>;
  839. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  840. #thermal-sensor-cells = <0>;
  841. };
  842.  
  843. uart0: serial@1c28000 {
  844. compatible = "snps,dw-apb-uart";
  845. reg = <0x01c28000 0x400>;
  846. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  847. reg-shift = <2>;
  848. reg-io-width = <4>;
  849. clocks = <&ccu CLK_APB2_UART0>;
  850. resets = <&ccu RST_APB2_UART0>;
  851. dmas = <&dma 6>, <&dma 6>;
  852. dma-names = "rx", "tx";
  853. status = "disabled";
  854. };
  855.  
  856. uart1: serial@1c28400 {
  857. compatible = "snps,dw-apb-uart";
  858. reg = <0x01c28400 0x400>;
  859. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  860. reg-shift = <2>;
  861. reg-io-width = <4>;
  862. clocks = <&ccu CLK_APB2_UART1>;
  863. resets = <&ccu RST_APB2_UART1>;
  864. dmas = <&dma 7>, <&dma 7>;
  865. dma-names = "rx", "tx";
  866. status = "disabled";
  867. };
  868.  
  869. uart2: serial@1c28800 {
  870. compatible = "snps,dw-apb-uart";
  871. reg = <0x01c28800 0x400>;
  872. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  873. reg-shift = <2>;
  874. reg-io-width = <4>;
  875. clocks = <&ccu CLK_APB2_UART2>;
  876. resets = <&ccu RST_APB2_UART2>;
  877. dmas = <&dma 8>, <&dma 8>;
  878. dma-names = "rx", "tx";
  879. status = "disabled";
  880. };
  881.  
  882. uart3: serial@1c28c00 {
  883. compatible = "snps,dw-apb-uart";
  884. reg = <0x01c28c00 0x400>;
  885. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  886. reg-shift = <2>;
  887. reg-io-width = <4>;
  888. clocks = <&ccu CLK_APB2_UART3>;
  889. resets = <&ccu RST_APB2_UART3>;
  890. dmas = <&dma 9>, <&dma 9>;
  891. dma-names = "rx", "tx";
  892. status = "disabled";
  893. };
  894.  
  895. uart4: serial@1c29000 {
  896. compatible = "snps,dw-apb-uart";
  897. reg = <0x01c29000 0x400>;
  898. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  899. reg-shift = <2>;
  900. reg-io-width = <4>;
  901. clocks = <&ccu CLK_APB2_UART4>;
  902. resets = <&ccu RST_APB2_UART4>;
  903. dmas = <&dma 10>, <&dma 10>;
  904. dma-names = "rx", "tx";
  905. status = "disabled";
  906. };
  907.  
  908. uart5: serial@1c29400 {
  909. compatible = "snps,dw-apb-uart";
  910. reg = <0x01c29400 0x400>;
  911. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  912. reg-shift = <2>;
  913. reg-io-width = <4>;
  914. clocks = <&ccu CLK_APB2_UART5>;
  915. resets = <&ccu RST_APB2_UART5>;
  916. dmas = <&dma 22>, <&dma 22>;
  917. dma-names = "rx", "tx";
  918. status = "disabled";
  919. };
  920.  
  921. /* CSI Connector */
  922. i2c0: i2c@1c2ac00 {
  923. compatible = "allwinner,sun6i-a31-i2c";
  924. reg = <0x01c2ac00 0x400>;
  925. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  926. clocks = <&ccu CLK_APB2_I2C0>;
  927. resets = <&ccu RST_APB2_I2C0>;
  928. #address-cells = <1>;
  929. #size-cells = <0>;
  930. pinctrl-names = "default";
  931. pinctrl-0 = <&i2c0_pins_a>;
  932. status = "disabled";
  933. };
  934.  
  935. /* LVDS Connector */
  936. i2c1: i2c@1c2b000 {
  937. compatible = "allwinner,sun6i-a31-i2c";
  938. reg = <0x01c2b000 0x400>;
  939. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  940. clocks = <&ccu CLK_APB2_I2C1>;
  941. resets = <&ccu RST_APB2_I2C1>;
  942. #address-cells = <1>;
  943. #size-cells = <0>;
  944. pinctrl-names = "default";
  945. pinctrl-0 = <&i2c1_pins_a>;
  946. status = "disabled";
  947. };
  948.  
  949. /* GPIO Connector */
  950. i2c2: i2c@1c2b400 {
  951. compatible = "allwinner,sun6i-a31-i2c";
  952. reg = <0x01c2b400 0x400>;
  953. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  954. clocks = <&ccu CLK_APB2_I2C2>;
  955. resets = <&ccu RST_APB2_I2C2>;
  956. #address-cells = <1>;
  957. #size-cells = <0>;
  958. pinctrl-names = "default";
  959. pinctrl-0 = <&i2c2_pins_a>;
  960. status = "disabled";
  961. };
  962.  
  963. i2c3: i2c@1c2b800 {
  964. compatible = "allwinner,sun6i-a31-i2c";
  965. reg = <0x01c2b800 0x400>;
  966. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  967. clocks = <&ccu CLK_APB2_I2C3>;
  968. resets = <&ccu RST_APB2_I2C3>;
  969. #address-cells = <1>;
  970. #size-cells = <0>;
  971. status = "disabled";
  972. };
  973.  
  974. gmac: ethernet@1c30000 {
  975. compatible = "allwinner,sun7i-a20-gmac";
  976. reg = <0x01c30000 0x1054>;
  977. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  978. interrupt-names = "macirq";
  979. clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
  980. clock-names = "stmmaceth", "allwinner_gmac_tx";
  981. resets = <&ccu RST_AHB1_EMAC>;
  982. reset-names = "stmmaceth";
  983. snps,pbl = <2>;
  984. snps,fixed-burst;
  985. snps,force_sf_dma_mode;
  986. status = "disabled";
  987. #address-cells = <1>;
  988. #size-cells = <0>;
  989. };
  990.  
  991. crypto: crypto-engine@1c15000 {
  992. compatible = "allwinner,sun6i-a31-crypto",
  993. "allwinner,sun4i-a10-crypto";
  994. reg = <0x01c15000 0x1000>;
  995. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  996. clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
  997. clock-names = "ahb", "mod";
  998. resets = <&ccu RST_AHB1_SS>;
  999. reset-names = "ahb";
  1000. };
  1001.  
  1002. codec: codec@1c22c00 {
  1003. #sound-dai-cells = <0>;
  1004. compatible = "allwinner,sun6i-a31-codec";
  1005. reg = <0x01c22c00 0x400>;
  1006. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  1007. clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
  1008. clock-names = "apb", "codec";
  1009. resets = <&ccu RST_APB1_CODEC>;
  1010. dmas = <&dma 15>, <&dma 15>;
  1011. dma-names = "rx", "tx";
  1012. status = "disabled";
  1013. };
  1014.  
  1015. timer@1c60000 {
  1016. compatible = "allwinner,sun6i-a31-hstimer",
  1017. "allwinner,sun7i-a20-hstimer";
  1018. reg = <0x01c60000 0x1000>;
  1019. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  1020. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  1021. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  1022. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  1023. clocks = <&ccu CLK_AHB1_HSTIMER>;
  1024. resets = <&ccu RST_AHB1_HSTIMER>;
  1025. };
  1026.  
  1027. spi0: spi@1c68000 {
  1028. compatible = "allwinner,sun6i-a31-spi";
  1029. reg = <0x01c68000 0x1000>;
  1030. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  1031. clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
  1032. clock-names = "ahb", "mod";
  1033. dmas = <&dma 23>, <&dma 23>;
  1034. dma-names = "rx", "tx";
  1035. resets = <&ccu RST_AHB1_SPI0>;
  1036. status = "disabled";
  1037. };
  1038.  
  1039. spi1: spi@1c69000 {
  1040. compatible = "allwinner,sun6i-a31-spi";
  1041. reg = <0x01c69000 0x1000>;
  1042. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  1043. clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
  1044. clock-names = "ahb", "mod";
  1045. dmas = <&dma 24>, <&dma 24>;
  1046. dma-names = "rx", "tx";
  1047. resets = <&ccu RST_AHB1_SPI1>;
  1048. pinctrl-names = "default";
  1049. pinctrl-0 = <&spi1_pins_a>;
  1050. status = "disabled";
  1051. };
  1052.  
  1053. spi2: spi@1c6a000 {
  1054. compatible = "allwinner,sun6i-a31-spi";
  1055. reg = <0x01c6a000 0x1000>;
  1056. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  1057. clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
  1058. clock-names = "ahb", "mod";
  1059. dmas = <&dma 25>, <&dma 25>;
  1060. dma-names = "rx", "tx";
  1061. resets = <&ccu RST_AHB1_SPI2>;
  1062. pinctrl-names = "default";
  1063. pinctrl-0 = <&spi2_pins_a>;
  1064. status = "disabled";
  1065. };
  1066.  
  1067. spi3: spi@1c6b000 {
  1068. compatible = "allwinner,sun6i-a31-spi";
  1069. reg = <0x01c6b000 0x1000>;
  1070. interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  1071. clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
  1072. clock-names = "ahb", "mod";
  1073. dmas = <&dma 26>, <&dma 26>;
  1074. dma-names = "rx", "tx";
  1075. resets = <&ccu RST_AHB1_SPI3>;
  1076. status = "disabled";
  1077. };
  1078.  
  1079. gic: interrupt-controller@1c81000 {
  1080. compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  1081. reg = <0x01c81000 0x1000>,
  1082. <0x01c82000 0x2000>,
  1083. <0x01c84000 0x2000>,
  1084. <0x01c86000 0x2000>;
  1085. interrupt-controller;
  1086. #interrupt-cells = <3>;
  1087. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  1088. };
  1089.  
  1090. fe0: display-frontend@1e00000 {
  1091. compatible = "allwinner,sun6i-a31-display-frontend";
  1092. reg = <0x01e00000 0x20000>;
  1093. interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
  1094. clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
  1095. <&ccu CLK_DRAM_FE0>;
  1096. clock-names = "ahb", "mod",
  1097. "ram";
  1098. resets = <&ccu RST_AHB1_FE0>;
  1099.  
  1100. ports {
  1101. #address-cells = <1>;
  1102. #size-cells = <0>;
  1103.  
  1104. fe0_out: port@1 {
  1105. #address-cells = <1>;
  1106. #size-cells = <0>;
  1107. reg = <1>;
  1108.  
  1109. fe0_out_be0: endpoint@0 {
  1110. reg = <0>;
  1111. remote-endpoint = <&be0_in_fe0>;
  1112. };
  1113.  
  1114. fe0_out_be1: endpoint@1 {
  1115. reg = <1>;
  1116. remote-endpoint = <&be1_in_fe0>;
  1117. };
  1118. };
  1119. };
  1120. };
  1121.  
  1122. fe1: display-frontend@1e20000 {
  1123. compatible = "allwinner,sun6i-a31-display-frontend";
  1124. reg = <0x01e20000 0x20000>;
  1125. interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  1126. clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
  1127. <&ccu CLK_DRAM_FE1>;
  1128. clock-names = "ahb", "mod",
  1129. "ram";
  1130. resets = <&ccu RST_AHB1_FE1>;
  1131.  
  1132. ports {
  1133. #address-cells = <1>;
  1134. #size-cells = <0>;
  1135.  
  1136. fe1_out: port@1 {
  1137. #address-cells = <1>;
  1138. #size-cells = <0>;
  1139. reg = <1>;
  1140.  
  1141. fe1_out_be0: endpoint@0 {
  1142. reg = <0>;
  1143. remote-endpoint = <&be0_in_fe1>;
  1144. };
  1145.  
  1146. fe1_out_be1: endpoint@1 {
  1147. reg = <1>;
  1148. remote-endpoint = <&be1_in_fe1>;
  1149. };
  1150. };
  1151. };
  1152. };
  1153.  
  1154. be1: display-backend@1e40000 {
  1155. compatible = "allwinner,sun6i-a31-display-backend";
  1156. reg = <0x01e40000 0x10000>;
  1157. interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  1158. clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
  1159. <&ccu CLK_DRAM_BE1>;
  1160. clock-names = "ahb", "mod",
  1161. "ram";
  1162. resets = <&ccu RST_AHB1_BE1>;
  1163.  
  1164. assigned-clocks = <&ccu CLK_BE1>;
  1165. assigned-clock-rates = <300000000>;
  1166.  
  1167. ports {
  1168. #address-cells = <1>;
  1169. #size-cells = <0>;
  1170.  
  1171. be1_in: port@0 {
  1172. #address-cells = <1>;
  1173. #size-cells = <0>;
  1174. reg = <0>;
  1175.  
  1176. be1_in_fe0: endpoint@0 {
  1177. reg = <0>;
  1178. remote-endpoint = <&fe0_out_be1>;
  1179. };
  1180.  
  1181. be1_in_fe1: endpoint@1 {
  1182. reg = <1>;
  1183. remote-endpoint = <&fe1_out_be1>;
  1184. };
  1185. };
  1186.  
  1187. be1_out: port@1 {
  1188. #address-cells = <1>;
  1189. #size-cells = <0>;
  1190. reg = <1>;
  1191.  
  1192. be1_out_drc1: endpoint@1 {
  1193. reg = <1>;
  1194. remote-endpoint = <&drc1_in_be1>;
  1195. };
  1196. };
  1197. };
  1198. };
  1199.  
  1200. drc1: drc@1e50000 {
  1201. compatible = "allwinner,sun6i-a31-drc";
  1202. reg = <0x01e50000 0x10000>;
  1203. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  1204. clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
  1205. <&ccu CLK_DRAM_DRC1>;
  1206. clock-names = "ahb", "mod",
  1207. "ram";
  1208. resets = <&ccu RST_AHB1_DRC1>;
  1209.  
  1210. assigned-clocks = <&ccu CLK_IEP_DRC1>;
  1211. assigned-clock-rates = <300000000>;
  1212.  
  1213. ports {
  1214. #address-cells = <1>;
  1215. #size-cells = <0>;
  1216.  
  1217. drc1_in: port@0 {
  1218. #address-cells = <1>;
  1219. #size-cells = <0>;
  1220. reg = <0>;
  1221.  
  1222. drc1_in_be1: endpoint@1 {
  1223. reg = <1>;
  1224. remote-endpoint = <&be1_out_drc1>;
  1225. };
  1226. };
  1227.  
  1228. drc1_out: port@1 {
  1229. #address-cells = <1>;
  1230. #size-cells = <0>;
  1231. reg = <1>;
  1232.  
  1233. drc1_out_tcon0: endpoint@0 {
  1234. reg = <0>;
  1235. remote-endpoint = <&tcon0_in_drc1>;
  1236. };
  1237.  
  1238. drc1_out_tcon1: endpoint@1 {
  1239. reg = <1>;
  1240. remote-endpoint = <&tcon1_in_drc1>;
  1241. };
  1242. };
  1243. };
  1244. };
  1245.  
  1246. be0: display-backend@1e60000 {
  1247. compatible = "allwinner,sun6i-a31-display-backend";
  1248. reg = <0x01e60000 0x10000>;
  1249. interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  1250. clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
  1251. <&ccu CLK_DRAM_BE0>;
  1252. clock-names = "ahb", "mod",
  1253. "ram";
  1254. resets = <&ccu RST_AHB1_BE0>;
  1255.  
  1256. assigned-clocks = <&ccu CLK_BE0>;
  1257. assigned-clock-rates = <300000000>;
  1258.  
  1259. ports {
  1260. #address-cells = <1>;
  1261. #size-cells = <0>;
  1262.  
  1263. be0_in: port@0 {
  1264. #address-cells = <1>;
  1265. #size-cells = <0>;
  1266. reg = <0>;
  1267.  
  1268. be0_in_fe0: endpoint@0 {
  1269. reg = <0>;
  1270. remote-endpoint = <&fe0_out_be0>;
  1271. };
  1272.  
  1273. be0_in_fe1: endpoint@1 {
  1274. reg = <1>;
  1275. remote-endpoint = <&fe1_out_be0>;
  1276. };
  1277. };
  1278.  
  1279. be0_out: port@1 {
  1280. #address-cells = <1>;
  1281. #size-cells = <0>;
  1282. reg = <1>;
  1283.  
  1284. be0_out_drc0: endpoint@0 {
  1285. reg = <0>;
  1286. remote-endpoint = <&drc0_in_be0>;
  1287. };
  1288. };
  1289. };
  1290. };
  1291.  
  1292. drc0: drc@1e70000 {
  1293. compatible = "allwinner,sun6i-a31-drc";
  1294. reg = <0x01e70000 0x10000>;
  1295. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  1296. clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
  1297. <&ccu CLK_DRAM_DRC0>;
  1298. clock-names = "ahb", "mod",
  1299. "ram";
  1300. resets = <&ccu RST_AHB1_DRC0>;
  1301.  
  1302. assigned-clocks = <&ccu CLK_IEP_DRC0>;
  1303. assigned-clock-rates = <300000000>;
  1304.  
  1305. ports {
  1306. #address-cells = <1>;
  1307. #size-cells = <0>;
  1308.  
  1309. drc0_in: port@0 {
  1310. #address-cells = <1>;
  1311. #size-cells = <0>;
  1312. reg = <0>;
  1313.  
  1314. drc0_in_be0: endpoint@0 {
  1315. reg = <0>;
  1316. remote-endpoint = <&be0_out_drc0>;
  1317. };
  1318. };
  1319.  
  1320. drc0_out: port@1 {
  1321. #address-cells = <1>;
  1322. #size-cells = <0>;
  1323. reg = <1>;
  1324.  
  1325. drc0_out_tcon0: endpoint@0 {
  1326. reg = <0>;
  1327. remote-endpoint = <&tcon0_in_drc0>;
  1328. };
  1329.  
  1330. drc0_out_tcon1: endpoint@1 {
  1331. reg = <1>;
  1332. remote-endpoint = <&tcon1_in_drc0>;
  1333. };
  1334. };
  1335. };
  1336. };
  1337.  
  1338. rtc: rtc@1f00000 {
  1339. compatible = "allwinner,sun6i-a31-rtc";
  1340. reg = <0x01f00000 0x54>;
  1341. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  1342. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  1343. };
  1344.  
  1345. nmi_intc: interrupt-controller@1f00c00 {
  1346. compatible = "allwinner,sun6i-a31-r-intc";
  1347. interrupt-controller;
  1348. #interrupt-cells = <2>;
  1349. reg = <0x01f00c00 0x400>;
  1350. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  1351. };
  1352.  
  1353. prcm@1f01400 {
  1354. compatible = "allwinner,sun6i-a31-prcm";
  1355. reg = <0x01f01400 0x200>;
  1356.  
  1357. ar100: ar100_clk {
  1358. compatible = "allwinner,sun6i-a31-ar100-clk";
  1359. #clock-cells = <0>;
  1360. clocks = <&osc32k>, <&osc24M>,
  1361. <&ccu CLK_PLL_PERIPH>,
  1362. <&ccu CLK_PLL_PERIPH>;
  1363. clock-output-names = "ar100";
  1364. };
  1365.  
  1366. ahb0: ahb0_clk {
  1367. compatible = "fixed-factor-clock";
  1368. #clock-cells = <0>;
  1369. clock-div = <1>;
  1370. clock-mult = <1>;
  1371. clocks = <&ar100>;
  1372. clock-output-names = "ahb0";
  1373. };
  1374.  
  1375. apb0: apb0_clk {
  1376. compatible = "allwinner,sun6i-a31-apb0-clk";
  1377. #clock-cells = <0>;
  1378. clocks = <&ahb0>;
  1379. clock-output-names = "apb0";
  1380. };
  1381.  
  1382. apb0_gates: apb0_gates_clk {
  1383. compatible = "allwinner,sun6i-a31-apb0-gates-clk";
  1384. #clock-cells = <1>;
  1385. clocks = <&apb0>;
  1386. clock-output-names = "apb0_pio", "apb0_ir",
  1387. "apb0_timer", "apb0_p2wi",
  1388. "apb0_uart", "apb0_1wire",
  1389. "apb0_i2c";
  1390. };
  1391.  
  1392. ir_clk: ir_clk {
  1393. #clock-cells = <0>;
  1394. compatible = "allwinner,sun4i-a10-mod0-clk";
  1395. clocks = <&osc32k>, <&osc24M>;
  1396. clock-output-names = "ir";
  1397. };
  1398.  
  1399. apb0_rst: apb0_rst {
  1400. compatible = "allwinner,sun6i-a31-clock-reset";
  1401. #reset-cells = <1>;
  1402. };
  1403. };
  1404.  
  1405. cpucfg@1f01c00 {
  1406. compatible = "allwinner,sun6i-a31-cpuconfig";
  1407. reg = <0x01f01c00 0x300>;
  1408. };
  1409.  
  1410. ir: ir@1f02000 {
  1411. compatible = "allwinner,sun5i-a13-ir";
  1412. clocks = <&apb0_gates 1>, <&ir_clk>;
  1413. clock-names = "apb", "ir";
  1414. resets = <&apb0_rst 1>;
  1415. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  1416. reg = <0x01f02000 0x40>;
  1417. status = "disabled";
  1418. };
  1419.  
  1420. r_pio: pinctrl@1f02c00 {
  1421. compatible = "allwinner,sun6i-a31-r-pinctrl";
  1422. reg = <0x01f02c00 0x400>;
  1423. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
  1424. <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  1425. clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
  1426. clock-names = "apb", "hosc", "losc";
  1427. resets = <&apb0_rst 0>;
  1428. gpio-controller;
  1429. interrupt-controller;
  1430. #interrupt-cells = <3>;
  1431. #size-cells = <0>;
  1432. #gpio-cells = <3>;
  1433.  
  1434. ir_pins_a: ir@0 {
  1435. pins = "PL4";
  1436. function = "s_ir";
  1437. };
  1438.  
  1439. p2wi_pins: p2wi {
  1440. pins = "PL0", "PL1";
  1441. function = "s_p2wi";
  1442. };
  1443. };
  1444.  
  1445. p2wi: i2c@1f03400 {
  1446. compatible = "allwinner,sun6i-a31-p2wi";
  1447. reg = <0x01f03400 0x400>;
  1448. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  1449. clocks = <&apb0_gates 3>;
  1450. clock-frequency = <100000>;
  1451. resets = <&apb0_rst 3>;
  1452. pinctrl-names = "default";
  1453. pinctrl-0 = <&p2wi_pins>;
  1454. status = "disabled";
  1455. #address-cells = <1>;
  1456. #size-cells = <0>;
  1457. };
  1458. };
  1459. };
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement
Public Pastes
Advertisement
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!